b0687062bd
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me> Link: https://github.com/openwrt/openwrt/pull/21019 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
82 lines
2.8 KiB
Diff
82 lines
2.8 KiB
Diff
From 249b78298078448a699c39356d27d8183af4b281 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Tue, 25 Feb 2025 09:04:07 +0100
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Subject: [PATCH] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581
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SoC
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Configure PBus base address and address mask to allow the hw
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to detect if a given address is accessible on PCIe controller.
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Fixes: f6ab898356dd ("PCI: mediatek-gen3: Add Airoha EN7581 support")
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Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/20250225-en7581-pcie-pbus-csr-v4-2-24324382424a@kernel.org
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Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
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---
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drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++++-
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1 file changed, 27 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pcie-mediatek-gen3.c
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+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
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@@ -15,6 +15,7 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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+#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_device.h>
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@@ -24,6 +25,7 @@
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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+#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "../pci.h"
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@@ -885,9 +887,13 @@ static int mtk_pcie_parse_port(struct mt
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static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
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{
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+ struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
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struct device *dev = pcie->dev;
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+ struct resource_entry *entry;
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+ struct regmap *pbus_regmap;
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+ u32 val, args[2], size;
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+ resource_size_t addr;
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int err;
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- u32 val;
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/*
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* The controller may have been left out of reset by the bootloader
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@@ -900,6 +906,26 @@ static int mtk_pcie_en7581_power_up(stru
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msleep(PCIE_EN7581_RESET_TIME_MS);
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/*
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+ * Configure PBus base address and base address mask to allow the
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+ * hw to detect if a given address is accessible on PCIe controller.
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+ */
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+ pbus_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node,
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+ "mediatek,pbus-csr",
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+ ARRAY_SIZE(args),
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+ args);
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+ if (IS_ERR(pbus_regmap))
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+ return PTR_ERR(pbus_regmap);
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+
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+ entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
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+ if (!entry)
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+ return -ENODEV;
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+
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+ addr = entry->res->start - entry->offset;
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+ regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
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+ size = lower_32_bits(resource_size(entry->res));
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+ regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size)));
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+
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+ /*
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* Unlike the other MediaTek Gen3 controllers, the Airoha EN7581
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* requires PHY initialization and power-on before PHY reset deassert.
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*/
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