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ce7a5037f3
openwrt/target/linux/realtek/dts/rtl9313_zyxel_xs1930-12f.dts
Jonas Jelonek ce7a5037f3 realtek: make LED set config for XS1930 more generic 
The led_set node was previously duplicated in the per-device DTS for
-10/-12HP and -12F, even though all three share the same Base-T LED
encoding. Move the shared led_set with the Base-T mapping into the
common DTSI as set 0, and have XS1930-12F append its SFP-port mapping
as led_set1 via a property override. Swap the led-set index on the
-12F ports accordingly so SFP ports use set 1 and the two Base-T
ports use set 0.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23428
Signed-off-by: Robert Marko <robimarko@gmail.com>
2026-05-21 12:08:42 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
#include "rtl9313_zyxel_xs1930.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/phy/phy.h>
/ {
compatible = "zyxel,xs1930-12f", "realtek,rtl9313-soc";
model = "Zyxel XS1930-12F";
sfp1: sfp-p1 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 36 GPIO_ACTIVE_HIGH>;
};
sfp2: sfp-p2 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>;
};
sfp3: sfp-p3 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
los-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
sfp4: sfp-p4 {
compatible = "sff,sfp";
i2c-bus = <&i2c3>;
los-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 6 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
};
sfp5: sfp-p5 {
compatible = "sff,sfp";
i2c-bus = <&i2c4>;
los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 7 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
};
sfp6: sfp-p6 {
compatible = "sff,sfp";
i2c-bus = <&i2c5>;
los-gpio = <&gpio1 34 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 29 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
sfp7: sfp-p7 {
compatible = "sff,sfp";
i2c-bus = <&i2c6>;
los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 31 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
};
sfp8: sfp-p8 {
compatible = "sff,sfp";
i2c-bus = <&i2c7>;
los-gpio = <&gpio1 32 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
};
sfp9: sfp-p9 {
compatible = "sff,sfp";
i2c-bus = <&i2c8>;
los-gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 11 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
};
sfp10: sfp-p10 {
compatible = "sff,sfp";
i2c-bus = <&i2c9>;
los-gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
};
};
&fan0 { gpios = <&gpio1 35 GPIO_ACTIVE_HIGH>; };
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_jtag>,
<&pinmux_disable_led_sync>;
};
&i2c_mst1 {
status = "okay";
i2c0: i2c@0 {
reg = <0>;
};
i2c1: i2c@1 {
reg = <1>;
};
i2c2: i2c@2 {
reg = <2>;
};
i2c3: i2c@3 {
reg = <3>;
};
i2c4: i2c@4 {
reg = <4>;
};
i2c5: i2c@5 {
reg = <5>;
};
};
&i2c_mst2 {
status = "okay";
i2c6: i2c@6 {
reg = <6>;
};
i2c7: i2c@7 {
reg = <7>;
};
i2c8: i2c@8 {
reg = <8>;
};
i2c9: i2c@9 {
reg = <9>;
};
i2c11: i2c@b {
reg = <0xb>;
gpio2: pca9555@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/* These GPIOs must be held low to activate SFP slots.
* Otherwise, neither power, signals nor I2C work.
*/
sfp_enable_hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>, /* SFP1 */
<1 GPIO_ACTIVE_LOW>, /* SFP2 */
<2 GPIO_ACTIVE_LOW>, /* SFP3 */
<3 GPIO_ACTIVE_LOW>, /* SFP4 */
<4 GPIO_ACTIVE_LOW>, /* SFP5 */
<5 GPIO_ACTIVE_LOW>, /* SFP6 */
<6 GPIO_ACTIVE_LOW>, /* SFP7 */
<7 GPIO_ACTIVE_LOW>, /* SFP8 */
<8 GPIO_ACTIVE_LOW>, /* SFP9 */
<9 GPIO_ACTIVE_LOW>; /* SFP10 */
output-high;
line-name = "enable-sfp-slots";
};
};
lm96000: lm96000@2e {
compatible = "national,lm85";
reg = <0x2e>;
};
};
};
&led_pwr_green { gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; };
&led_pwr_red { gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; };
&led_cloud_green { gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; };
&led_cloud_red { gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; };
&led_locator { gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; };
&led_set {
/* SFP ports */
led_set1 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)>;
};
&mdio_aux {
status = "okay";
gpio1: gpio@1f {
compatible = "realtek,rtl8231";
reg = <0x1f>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio1 0 0 37>;
led-controller {
compatible = "realtek,rtl8231-leds";
status = "disabled";
};
};
};
&mdio_ctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_mdc_mdio_1>,
<&pinmux_enable_mdc_mdio_2>;
};
&mdio_bus1 {
PHY_C45(54, 0) /* AQR113C */
};
&mdio_bus2 {
PHY_C45(55, 8) /* AQR113C */
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SFP(0, 1, 2, 1, 1)
SWITCH_PORT_SFP(8, 2, 3, 1, 2)
SWITCH_PORT_SFP(16, 3, 4, 1, 3)
SWITCH_PORT_SFP(24, 4, 5, 1, 4)
SWITCH_PORT_SFP(32, 5, 6, 1, 5)
SWITCH_PORT_SFP(40, 6, 7, 1, 6)
SWITCH_PORT_SFP(48, 7, 8, 1, 7)
SWITCH_PORT_SFP(50, 8, 9, 1, 8)
SWITCH_PORT_SFP(52, 9, 10, 1, 9)
SWITCH_PORT_SFP(53, 10, 11, 1, 10)
/* Base-T ports */
SWITCH_PORT_LED(54, 11, 12, 0, usxgmii)
SWITCH_PORT_LED(55, 12, 13, 0, usxgmii)
/* CPU port */
port@56 {
reg = <56>;
ethernet = <&ethernet0>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&port54 {
managed = "in-band-status";
};
&port55 {
managed = "in-band-status";
};
&serdes2 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes3 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes4 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes5 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes6 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes7 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes8 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes9 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes10 {
tx-polarity = <PHY_POL_INVERT>;
};
&serdes11 {
tx-polarity = <PHY_POL_INVERT>;
};
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