After the RTL8261N asserts a reset, the MDIO bus becomes temporarily
unavailable during the chip's reinitialization sequence. Any subsequent
read or write issued before the PHY has stabilized will fail.
Add a 30ms delay after triggering the reset to ensure the chip is reachable
via MDIO before resuming communication.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/23076
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
51992c87c8