eb769c6fc3
Add IPQ6018 support to the upstream CMN PLL driver. The CMN PLL at 0x9b000 generates the 12 GHz base clock feeding the networking subsystem. Its output clocks (bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at 416.5 MHz) replace the previous fixed-clock stubs and are found by GCC via global clock name lookup. Signed-off-by: John Crispin <john@phrozen.org> |
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| .. | ||
| imagebuilder | ||
| linux | ||
| llvm-bpf | ||
| sdk | ||
| toolchain | ||
| Config.in | ||
| Makefile | ||