A recent target-wide change missed the DTSI for a few devices causing a
build issue for RTL930x. Fix that.
Fixes: 43562f97e7 ("realtek: dts: add link index cell to pcs-handle phandles")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
215 lines
3.9 KiB
Plaintext
215 lines
3.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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};
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keys {
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compatible = "gpio-keys";
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button-reset {
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label = "reset";
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gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_sys: led-0 {
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gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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};
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led_set {
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compatible = "realtek,rtl9300-leds";
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led_set0 = <
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(RTL93XX_LED_SET_NONE)
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(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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>;
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};
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sfp0: sfp-p1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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mod-def0-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <2000>;
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#thermal-sensor-cells = <0>;
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};
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sfp1: sfp-p2 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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mod-def0-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <2000>;
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#thermal-sensor-cells = <0>;
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};
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sfp2: sfp-p3 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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mod-def0-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <2000>;
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#thermal-sensor-cells = <0>;
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};
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sfp3: sfp-p4 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c3>;
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mod-def0-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <2000>;
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#thermal-sensor-cells = <0>;
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};
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};
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&i2c_mst1 {
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status = "okay";
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i2c0: i2c@0 { reg = <0>; };
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i2c1: i2c@1 { reg = <1>; };
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i2c2: i2c@2 { reg = <2>; };
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i2c3: i2c@3 { reg = <3>; };
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* stock is LOADER */
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partition@0 {
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label = "u-boot";
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reg = <0x0000000 0x00e0000>;
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read-only;
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};
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/* stock is BDINFO */
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partition@e0000 {
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label = "u-boot-env";
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reg = <0x00e0000 0x0010000>;
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};
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/* stock is SYSINFO */
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partition@f0000 {
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label = "u-boot-env2";
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reg = <0x00f0000 0x0010000>;
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};
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/* stock is CFG JFFS2 */
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partition@100000 {
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label = "jffs";
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reg = <0x0100000 0x0100000>;
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};
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/* stock is LOG JFFS2 */
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partition@200000 {
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label = "jffs2";
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reg = <0x0200000 0x0100000>;
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};
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/* stock is RUNTIME and RUNTIME2
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* RUNTIME is <0x0300000 0x0e80000>
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* RUNTIME2 is <0x1180000 0x0e80000>
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*/
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partition@300000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x0300000 0x1d00000>;
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};
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};
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};
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};
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&mdio_bus0 {
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PHY_C45(26, 16)
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};
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&mdio_bus1 {
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PHY_C45(27, 0)
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};
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&mdio_bus2 {
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PHY_C45(24, 0)
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};
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&mdio_bus3 {
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PHY_C45(25, 16)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* SFP+ ports, lan1-4 */
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SWITCH_PORT_SFP(0, 1, 2, 0, 0)
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SWITCH_PORT_SFP(8, 2, 3, 0, 1)
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SWITCH_PORT_SFP(16, 3, 4, 0, 2)
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SWITCH_PORT_SFP(20, 4, 5, 0, 3)
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/* RJ45 ports, lan5-8 */
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SWITCH_PORT_LED(24, 5, 6, 0, 0, usxgmii)
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SWITCH_PORT_LED(25, 6, 7, 0, 0, usxgmii)
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SWITCH_PORT_LED(26, 7, 8, 0, 0, usxgmii)
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SWITCH_PORT_LED(27, 8, 9, 0, 0, usxgmii)
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/* CPU port */
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&thermal_zones {
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sfp-thermal {
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polling-delay-passive = <10000>;
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polling-delay = <10000>;
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thermal-sensors = <&sfp0>, <&sfp1>, <&sfp2>, <&sfp3>;
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trips {
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sfp-crit {
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temperature = <110000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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};
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};
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