1
1
openwrt/target/linux/realtek/dts/rtl9303_hasivo_f1100w-4sx-4xgt-common.dtsi
Jonas Jelonek ed2a36afae
realtek: fix macro usage in F1100W-4SX-4XGT DTSI
A recent target-wide change missed the DTSI for a few devices causing a
build issue for RTL930x. Fix that.

Fixes: 43562f97e7 ("realtek: dts: add link index cell to pcs-handle phandles")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-05-31 12:51:56 +00:00

215 lines
3.9 KiB
Plaintext

// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
#include "rtl930x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
};
chosen {
stdout-path = "serial0:38400n8";
};
keys {
compatible = "gpio-keys";
button-reset {
label = "reset";
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_sys: led-0 {
gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
};
};
led_set {
compatible = "realtek,rtl9300-leds";
led_set0 = <
(RTL93XX_LED_SET_NONE)
(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_5G |
RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
>;
};
sfp0: sfp-p1 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
mod-def0-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
#thermal-sensor-cells = <0>;
};
sfp1: sfp-p2 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
mod-def0-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
#thermal-sensor-cells = <0>;
};
sfp2: sfp-p3 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
mod-def0-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
#thermal-sensor-cells = <0>;
};
sfp3: sfp-p4 {
compatible = "sff,sfp";
i2c-bus = <&i2c3>;
mod-def0-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <2000>;
#thermal-sensor-cells = <0>;
};
};
&i2c_mst1 {
status = "okay";
i2c0: i2c@0 { reg = <0>; };
i2c1: i2c@1 { reg = <1>; };
i2c2: i2c@2 { reg = <2>; };
i2c3: i2c@3 { reg = <3>; };
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* stock is LOADER */
partition@0 {
label = "u-boot";
reg = <0x0000000 0x00e0000>;
read-only;
};
/* stock is BDINFO */
partition@e0000 {
label = "u-boot-env";
reg = <0x00e0000 0x0010000>;
};
/* stock is SYSINFO */
partition@f0000 {
label = "u-boot-env2";
reg = <0x00f0000 0x0010000>;
};
/* stock is CFG JFFS2 */
partition@100000 {
label = "jffs";
reg = <0x0100000 0x0100000>;
};
/* stock is LOG JFFS2 */
partition@200000 {
label = "jffs2";
reg = <0x0200000 0x0100000>;
};
/* stock is RUNTIME and RUNTIME2
* RUNTIME is <0x0300000 0x0e80000>
* RUNTIME2 is <0x1180000 0x0e80000>
*/
partition@300000 {
compatible = "openwrt,uimage", "denx,uimage";
label = "firmware";
reg = <0x0300000 0x1d00000>;
};
};
};
};
&mdio_bus0 {
PHY_C45(26, 16)
};
&mdio_bus1 {
PHY_C45(27, 0)
};
&mdio_bus2 {
PHY_C45(24, 0)
};
&mdio_bus3 {
PHY_C45(25, 16)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
/* SFP+ ports, lan1-4 */
SWITCH_PORT_SFP(0, 1, 2, 0, 0)
SWITCH_PORT_SFP(8, 2, 3, 0, 1)
SWITCH_PORT_SFP(16, 3, 4, 0, 2)
SWITCH_PORT_SFP(20, 4, 5, 0, 3)
/* RJ45 ports, lan5-8 */
SWITCH_PORT_LED(24, 5, 6, 0, 0, usxgmii)
SWITCH_PORT_LED(25, 6, 7, 0, 0, usxgmii)
SWITCH_PORT_LED(26, 7, 8, 0, 0, usxgmii)
SWITCH_PORT_LED(27, 8, 9, 0, 0, usxgmii)
/* CPU port */
port@28 {
ethernet = <&ethernet0>;
reg = <28>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&thermal_zones {
sfp-thermal {
polling-delay-passive = <10000>;
polling-delay = <10000>;
thermal-sensors = <&sfp0>, <&sfp1>, <&sfp2>, <&sfp3>;
trips {
sfp-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};