ed4b6ad372
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.18.25 Manually rebased: generic/pending-6.18/795-09-net-ethernet-mtk_ppe-offload-flows-to-MxL862xx-switc.patch All other patches automatically rebased via update_kernel.sh Build system: x86/64 Build-tested: x86/64-glibc Run-tested: x86/64-glibc Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/22890 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
116 lines
3.9 KiB
Diff
116 lines
3.9 KiB
Diff
From bc51c337a3147c4a02c743489885a6657bc5371c Mon Sep 17 00:00:00 2001
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From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
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Date: Wed, 27 Nov 2024 13:36:49 +0800
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Subject: [PATCH] net: ethernet: mtk_eth_soc: add hw dump for forced reset
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Without this patch, the ETH driver is unable to dump the registers
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before triggering a forced reset.
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Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 55 +++++++++++++++++++++
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1 files changed, 55 insertions(+)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -75,6 +75,7 @@ static const struct mtk_reg_map mtk_reg_
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.rx_ptr = 0x1900,
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.rx_cnt_cfg = 0x1904,
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.qcrx_ptr = 0x1908,
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+ .page = 0x19f0,
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.glo_cfg = 0x1a04,
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.rst_idx = 0x1a08,
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.delay_irq = 0x1a0c,
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@@ -141,6 +142,7 @@ static const struct mtk_reg_map mt7986_r
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.rx_ptr = 0x4500,
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.rx_cnt_cfg = 0x4504,
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.qcrx_ptr = 0x4508,
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+ .page = 0x45f0,
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.glo_cfg = 0x4604,
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.rst_idx = 0x4608,
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.delay_irq = 0x460c,
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@@ -192,6 +194,7 @@ static const struct mtk_reg_map mt7988_r
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.rx_ptr = 0x4500,
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.rx_cnt_cfg = 0x4504,
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.qcrx_ptr = 0x4508,
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+ .page = 0x45f0,
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.glo_cfg = 0x4604,
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.rst_idx = 0x4608,
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.delay_irq = 0x460c,
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@@ -4193,6 +4196,56 @@ static void mtk_set_mcr_max_rx(struct mt
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mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
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}
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+static void mtk_hw_dump_reg(struct mtk_eth *eth, char *name, u32 offset, u32 range)
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+{
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+ u32 cur = offset;
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+
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+ pr_info("\n==================== %s ====================\n", name);
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+ while (cur < offset + range) {
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+ pr_info("0x%08x: %08x %08x %08x %08x\n",
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+ cur, mtk_r32(eth, cur), mtk_r32(eth, cur + 0x4),
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+ mtk_r32(eth, cur + 0x8), mtk_r32(eth, cur + 0xc));
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+ cur += 0x10;
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+ }
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+}
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+
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+static void mtk_hw_dump(struct mtk_eth *eth)
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+{
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+ const struct mtk_reg_map *reg_map = eth->soc->reg_map;
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+ u32 id;
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+
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+ mtk_hw_dump_reg(eth, "FE", 0x0, 0x600);
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+ mtk_hw_dump_reg(eth, "FE", 0x1400, 0x300);
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+ mtk_hw_dump_reg(eth, "ADMA", reg_map->pdma.rx_ptr, 0x300);
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
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+ for (id = 0; id < eth->soc->num_tx_queues / MTK_QTX_PER_PAGE; id++) {
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+ mtk_w32(eth, id, reg_map->qdma.page);
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+ pr_info("\nQDMA PAGE:%x ", mtk_r32(eth, reg_map->qdma.page));
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+ mtk_hw_dump_reg(eth, "QDMA", reg_map->qdma.qtx_cfg, 0x100);
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+ mtk_w32(eth, 0, reg_map->qdma.page);
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+ }
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+ mtk_hw_dump_reg(eth, "QDMA", reg_map->qdma.rx_ptr, 0x300);
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+ }
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+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
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+ mtk_hw_dump_reg(eth, "WDMA0", reg_map->wdma_base[0], 0x400);
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+ mtk_hw_dump_reg(eth, "WDMA1", reg_map->wdma_base[1], 0x400);
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+ if (mtk_is_netsys_v3_or_greater(eth))
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+ mtk_hw_dump_reg(eth, "WDMA2", reg_map->wdma_base[2], 0x400);
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+ }
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+ mtk_hw_dump_reg(eth, "PPE0", reg_map->ppe_base + 0x200, 0x200);
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+ if (!mtk_is_netsys_v1(eth))
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+ mtk_hw_dump_reg(eth, "PPE1", reg_map->ppe_base + 0x600, 0x200);
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+ if (mtk_is_netsys_v3_or_greater(eth))
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+ mtk_hw_dump_reg(eth, "PPE2", reg_map->ppe_base + 0xE00, 0x200);
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+ mtk_hw_dump_reg(eth, "GMAC", 0x10000, 0x300);
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+ if (mtk_is_netsys_v3_or_greater(eth))
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+ mtk_hw_dump_reg(eth, "GMAC", 0x10300, 0x100);
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+ if (mtk_is_netsys_v3_or_greater(eth)) {
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+ mtk_hw_dump_reg(eth, "XGMAC0", 0x12000, 0x300);
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+ mtk_hw_dump_reg(eth, "XGMAC1", 0x13000, 0x300);
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+ }
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+}
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+
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static void mtk_hw_reset(struct mtk_eth *eth)
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{
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u32 val;
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@@ -4677,6 +4730,8 @@ static void mtk_pending_work(struct work
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rtnl_lock();
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set_bit(MTK_RESETTING, ð->state);
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+ mtk_hw_dump(eth);
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+
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mtk_prepare_for_reset(eth);
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mtk_wed_fe_reset();
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/* Run again reset preliminary configuration in order to avoid any
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -1200,6 +1200,7 @@ struct mtk_reg_map {
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u32 rx_ptr; /* rx base pointer */
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u32 rx_cnt_cfg; /* rx max count configuration */
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u32 qcrx_ptr; /* rx cpu pointer */
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+ u32 page; /* page configuration */
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u32 glo_cfg; /* global configuration */
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u32 rst_idx; /* reset index */
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u32 delay_irq; /* delay interrupt */
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