60a5f423b0
Add a qcom pinctrl fix for ipq4019 that marks the gpio function as a GPIO pin function. With Linux 6.18 strict pinmuxing, ipq40xx can otherwise hit conflicts when pins muxed to "gpio" are later requested by GPIO consumers. [1] This patch fixes that at the driver level and avoids DTS-side workarounds, same as it is done for other Qualcomm boards. [2] [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=cc85cb96e2e4 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=480dc1952404 Signed-off-by: Til Kaiser <mail@tk154.de> Link: https://github.com/openwrt/openwrt/pull/22930 Signed-off-by: Nick Hainke <vincent@systemli.org>
52 lines
2.0 KiB
Diff
52 lines
2.0 KiB
Diff
From 437579ad9804055132ad40ccc1ba0cc64dbd828b Mon Sep 17 00:00:00 2001
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From: Til Kaiser <mail@tk154.de>
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Date: Mon, 13 Apr 2026 10:29:20 +0200
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Subject: [PATCH] pinctrl: qcom: ipq4019: mark gpio as a GPIO pin function
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The qcom pinctrl core supports marking functions that represent GPIO mode
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via PINCTRL_GPIO_PINFUNCTION(), so that strict pinmuxing does not reject
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GPIO requests for pins that are muxed to the GPIO function.
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ipq4019 still describes its gpio function with QCA_PIN_FUNCTION(gpio),
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so it is not treated as a GPIO pin function. As a result, GPIO consumers
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can still conflict with pinctrl states that select the "gpio" function.
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Add a QCA_GPIO_PIN_FUNCTION() helper and use it for the ipq4019 gpio
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function, matching how the msm-based qcom drivers handle this.
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This allows ipq4019 to keep the GPIO-related pin configuration in DTS
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without tripping over strict pinmux ownership checks.
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Fixes: cc85cb96e2e4 ("pinctrl: qcom: make the pinmuxing strict")
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Signed-off-by: Til Kaiser <mail@tk154.de>
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---
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drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
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drivers/pinctrl/qcom/pinctrl-msm.h | 5 +++++
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2 files changed, 6 insertions(+), 1 deletion(-)
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--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
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@@ -480,7 +480,7 @@ static const struct pinfunction ipq4019_
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QCA_PIN_FUNCTION(blsp_uart0),
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QCA_PIN_FUNCTION(blsp_uart1),
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QCA_PIN_FUNCTION(chip_rst),
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- QCA_PIN_FUNCTION(gpio),
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+ QCA_GPIO_PIN_FUNCTION(gpio),
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QCA_PIN_FUNCTION(i2s_rx),
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QCA_PIN_FUNCTION(i2s_spdif_in),
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QCA_PIN_FUNCTION(i2s_spdif_out),
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--- a/drivers/pinctrl/qcom/pinctrl-msm.h
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
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@@ -39,6 +39,11 @@ struct pinctrl_pin_desc;
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fname##_groups, \
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ARRAY_SIZE(fname##_groups))
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+#define QCA_GPIO_PIN_FUNCTION(fname) \
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+ [qca_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \
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+ fname##_groups, \
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+ ARRAY_SIZE(fname##_groups))
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+
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/**
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* struct msm_pingroup - Qualcomm pingroup definition
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* @grp: Generic data of the pin group (name and pins)
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