This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/21078
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add define for kernel 6.18.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/21078
Signed-off-by: Robert Marko <robimarko@gmail.com>
On qca8k multi-CPU-port setups (e.g. qca8337 with ports 0+6 as CPU),
bridging switch user ports that use different conduits can make the host
reachable only from the ports tied to the last-programmed CPU port.
Add a pending kernel patch which makes qca8k merge CPU/DSA-port FDB
programming, so host FDB entries end up on all relevant CPU ports.
Fixes: openwrt/openwrt#17891
Signed-off-by: Kevin Staley <glaciertablet@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21317
Signed-off-by: Robert Marko <robimarko@gmail.com>
rtmdio_probe() is a do-it-all setup function. It creates one
control structure and one bus. In the future multiple busses
will be created. As a preparation carve out the bus specific
part into an individual probing function.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
Until now the central control structure is allocated via a call to
devm_mdiobus_alloc_size(). This will not be possible any longer when
multiple busses will be implemented in a future commit.
Relax that as follows:
- Define a new private "channel" structure for a mdio bus
- Allocate the central control structure with a dedicated alloc()
- Allocate only the channel structure during bus setup
- Link the channel to the central structure via chan->ctrl
Reorganize the probing function so that it becomes clearer that
the control structure is setup first and afterwards the bus is
registered.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add a new helper macro rtmdio_ctrl_from_bus that encapuslates
the current ctrl=bus->priv lookup. This is a preparation for
the future multi-channel driver architecture. With an upcoming
commit the structures will be changed as follows:
- ctrl: contains the generic data structurs
- chan: contains the channel specific structure
This will involve changing the pointers between them
old lookup chain: ctrl = bus->ctrl
new lookup chain: ctrl = bus->chan->ctrl
The helper macro allows to easily switch the lookup in one
central location. While we are here fix a whitespace issue.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
The topology setup is bus independent and can be derived completely
from the control structure. Adapt the call parameters accordingly.
The call location is quite confusing at the moment. Being no longer
dependent from the bus call it where it makes most sense. This is
directly after the mapping setup in rtmdio_map_ports(). Doing other
bus dependent setup between these two functions is not needed
any longer.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
The port specific attributes of the central control structure
have been moved over to a separate port structure. Do the same
for the (up to 4) busses. Establish a separate bus structure
that will hold data about each bus and use it in the control
structure. As a first usage type move the is_c45 attribute over.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
The phy_node attribute is defined per port. Move it into the new
port structure. Now it is clear that it belongs to the port.
While we are here rename it to dn (aka device_node) to align with
upstream style. As all usage locations must be adapted it makes
no sense to make two commits (relocate/rename) to change the
code twice.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
The smi_addr attribute is defined per port. Move it into the new
port structure. As the devices have a maximum of 56 addresses
save some space and convert it to type u8.
While we are here harden the mapping routine that reads these
addresses from the DTS. For this check the value that is read into
smi_addr. This is usually the MDIO standard 0..31. Sadly RTL839x
devices are an exception from that and allow addresses 0..51.
To avoid device specific if/then/else cases for now implement
a "light" consistency check.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
The smi_bus attribute is defined per port. Move it into the new
port structure. As the devices have a maximum of 4 busses save
some space and convert it to type u8.
While we are here fix a whitespace issue and rename the helper
variable in rtmdio_map_ports() to smi_bus to align with the
structure attribute.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
The raw attribute is defined per port. Move it into the new
port structure.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
The central control structure of the mdio bus holds several
attributes. These target two different objects. Some of them
are for the (up to 56) controller ports, some of them are for
the (up to 4) controller busses.
Establish a separate port structure that will hold data about
each port and use it in the control structure. As a first
usage type move the page attribute over.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22604
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport upstream driver and apply pending downstream patches to
support using the MaxLinear MxL86252 and MxL86282 switches.
The driver supports a native proprietary 8-byte DSA special tag format
(mxl862xx) as well as using an 802.1Q-based DSA tag (mxl862xx-8021q).
All basic bridge, VLAN and LAG operations are supported. A single port
can be used as mirror port. Hardware counters are made available as
ethtool stats or directly serve as interface counters (bytes,
packets).
The switch runs a complex ZephyrOS-based firmware on an integrated
ARC microcontroller, the driver uses the firmware management API over
MDIO to interact with the switch hardware.
Note that the firmware needs to be rather recent (WSP 1.0.78 or later)
to work well with this driver. It can be updated at runtime using devlink.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Add IPQ8074 support to the upstream CMN PLL driver. The CMN PLL block
is identical to IPQ6018 with the same output clocks (bias_pll_cc_clk
at 300 MHz and bias_pll_nss_noc_clk at 416.5 MHz).
Signed-off-by: John Crispin <john@phrozen.org>
Add IPQ6018 support to the upstream CMN PLL driver. The CMN PLL at
0x9b000 generates the 12 GHz base clock feeding the networking
subsystem. Its output clocks (bias_pll_cc_clk at 300 MHz and
bias_pll_nss_noc_clk at 416.5 MHz) replace the previous fixed-clock
stubs and are found by GCC via global clock name lookup.
Signed-off-by: John Crispin <john@phrozen.org>
The XO clock source is always-on in hardware and cannot be gated.
Without CLK_IS_CRITICAL, the CMN PLL runtime PM suspend cascades a
disable up to gcc_xo_clk_src, causing a branch status timeout warning.
The IPQ8074 GCC driver already marks this clock as critical.
Signed-off-by: John Crispin <john@phrozen.org>
This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000h-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000h-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000h-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000e-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000e-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000e-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000s-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000s-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000s-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
This allows us to use the full size of nand,
which extends ubi size from 64Mb to 122.25Mb.
1. Log in to the device and backup all the partitions,
especially unique "Factory" and "bdata" partitions
from System -> Backup / Flash Firmware -> Save mtdblock contents.
2. Install kmod-mtd-rw to unlock mtd partitions for writing
apk update && apk add kmod-mtd-rw && insmod mtd-rw i_want_a_brick=1
3. Write new OpenWrt (U-Boot Layout) "BL2" and "FIP":
mtd -e BL2 write openwrt-mediatek-filogic-cudy_wr3000p-v1-ubootmod-preloader.bin BL2
mtd -e FIP write openwrt-mediatek-filogic-cudy_wr3000p-v1-ubootmod-bl31-uboot.fip FIP
4. Set static IP on your PC: "192.168.1.254", gateway "192.168.1.1"
5. Serve openwrt-mediatek-filogic-cudy_wr3000p-v1-ubootmod-initramfs-recovery.itb
using TFTP server.
6. Connect Router LAN with PC LAN.
7. Cut off the power and re-engage, wait for TFTP recovery to complete.
8. After OpenWrt initramfs recovery has booted,
clean "/dev/mtd5" ubi partition to utilize maximum of free space:
ubidetach -p /dev/mtd5; ubiformat /dev/mtd5 -y; ubiattach -p /dev/mtd5
ubimkvol /dev/ubi0 -n 0 -N ubootenv -s 128KiB
ubimkvol /dev/ubi0 -n 1 -N ubootenv2 -s 128KiB
9. Perform sysupgrade.
Signed-off-by: Dmitry Mostovoy <stavultras@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21943
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use the common driver prefix for these two functions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22610
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Check for dev in driver remove gives no additional security. The
remove() function is only called if probe() succeeded. Probing
will always call platform_set_drvdata() in the good case. So
remove() will always find dev data via platform_get_drvdata().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22610
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The ethernet driver is only loaded via devicetree and makes use
of of_match_table. In this case the probing function is only
called if a matching compatible is set. So pdev->dev.of_node
can never be NULL.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22610
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Align the driver and matchtable naming convention to the new
rteth prefix. While we are here autogenerate the module name
by using KBUILD_MODNAME. This is common upstream practice.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22610
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Commit d52f7a4ca5 ("realtek: dts: new SWITCH_PORT_LED() macro") introduced
a new macro to simplify switch port definitions and introduces usage of
it for Zyxel XGS1X10-12 devices. However, this change added a DTS syntax
issue because:
> SWITCH_PORT_LED(...);
produces
> port@XX { ... };;
because the macro already includes a trailing semicolon. The DT compiler
doesn't like this so it fails with syntax error. Fix this by dropping the
trailing semicolons after macro usages.
Fixes: d52f7a4ca5 ("realtek: dts: new SWITCH_PORT_LED() macro")
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22614
Signed-off-by: Robert Marko <robimarko@gmail.com>
The 'phy-connection-type' property is unnecessary and can be removed.
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is a cosmetic change. The device uses the MT7992AV chip.
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL8261BE 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us),
but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a
minimum **SMI-ready time of 150ms** after nRESET release before the MDIO
(SMI) bus can be used.
Note: Essentially, the RTL8261N and RTL8261BE are architecturally identical
chips, so their initialization parameters should be consistent.
Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22575
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Previous changes refactored the hardware mode configuration for RTL930x
a lot. Now that this is in a better shape, one issue persists: missing
error propagation. Only parts of this function really propagate an
error, others are silently dropped. While this is a known driver-wide
issue, at least make it good here. Propagate the errors from functions
which apply configuration sequences to the caller.
Single writes are still left out on purpose, they need and will be
addressed later.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Decommission a helper for applying config/patch sequences for even/odd
SerDes. Most of these sequences were squashed due to marginal
difference, sharing a lot of common parts. For the marginal differences,
testing showed that the different values were already present on
even/odd. Since those are no reset/trigger bits but just configuration
values, writing them for both should do no harm.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Config/patch sequences have been reduced and merged by previous changes.
Now that we have a clearer view on them, we can see that there are still
several similarities between the even and odd variants. Some different
writes for even and odd SerDes remain but one can find out they don't
need to be separate. For example, a write to [0x29, 0x09] is missing for
odd SerDes but testing and a SerDes dump from a running configuration
show that the registers still hold the same value and changes do not
affect functionality. Thus, merge them too to get rid of a lot of
even/odd stuff.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Right now, the config sequences for XSGMII and USXGMII have been
stripped down to their essential parts. Still, they have redundancies.
The XSGMII sequences are 99% equal to the generic ANA_10G sequences
(except for a single write which is DFE/LEQ-related and changed during
calibration later anyway), thus we can drop them completely.
The USXGMII sequences contain the same sequences so they can be removed
there too, all being covered by applying the ANA_10G sequence for those
modes too. One different write (register [0x2e, 0x01]) is integrated into
the ANA_10G sequence since testing has shown that the value is either the
default for that register anyway, or set during SDK setup too for 10GR.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Move a few register writes from the ANA_10G patch sequences to the
configuration function. Those write are targeted at digital pages and do
not fully apply for *SGMII modes. To make the ANA_10G sequence really
just deal with analog pages and make it usable for *SGMII modes too,
move out the digital page writes.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
The patch/config sequences we took over from the SDK are partially
redundant, i.e. they share common parts which can be separated per
speed. For example, the config for 10GR contains the one for 2500Base-X
but we have a dedicated one for 2500Base-X. This is a first step to
modularize and reverse-engineer those sequences, and decrease the size
they claim.
The sequences are nearly exclusive ordered by ascending pages. This
suggests that those register/writes do not have a hidden function of
performing inline resets but rather are just configuration values.
Likely, they may be applied in rather arbitrary order. Splitting up the
sequences here assumes this is true and does some minor order changes.
Testing shows no behavioral change. Looking at [1] there are no relevant
reset or trigger bits affected by that. Suspiciously ordered writes have
mostly been kept though.
USXGMII setup needs to be adjusted too due to shared sequence parts.
[1] 82af3a36b7/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
The patch/config sequences for USXGMII modes contain a register write
which is explicitly labelled as "enable eee". To clean the sequences and
reduce duplication, move this specific write to the USXGMII
configuration function.
While at it, demystify this register write. From [1] we can see that
only a single bit needs to be set for controlling EEE instead of the
whole register. From testing it was seen that the register has a default
value of 0x445C after reset. Thus, there is no other operation hidden in
this write and we're safe to reduce it to setting just the EEE enable
bit.
[1] 82af3a36b7/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
USXGMII configuration is currently only performed via the patching
sequences although there's a dedicated function which configures several
parameters and assigns meaningful names to some register fields. It was
introduced in dca20f91ea ("realtek: add serdes patch for 10G_QXGMII")
but somewhat abandoned later due to a partial revert.
To improve the situation, prioritize usage of the function for USXGMII
variants and remove some parts from the patch sequences which seem to be
exclusive for USXGMII and thus can be covered by this function. Writes
to registers [0x6, 0xE], [0x6, 0x13] and [0x6, 0x14] can be dropped
completely because they are redundant. The bits really affected by
these writes (compared to the default register values aquired from a
dump) are overwritten below again. Testing on real hardware and USXGMII
supports this.
While at it, improve the style a bit and add comments explaining some of
the fields a bit more. Additionally, fix the call situation which
currently is dead code due to early exit. Provide two calls to the
mentioned functions but comment one of them to remain current
functionality. Names and meaning of fields is inferred from [1].
[1] 82af3a36b7/sources/rtk-dms1250/include/hal/phy/rtl8295_reg_def.h
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Start deconstructing the patch/config sequences by carving out two
specific writes which are common for non-USXGMII and are special because
they are not in analog SerDes pages.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Handle QSGMII config earlier within the configuration function as a
preparation for subsequent patches in this area. Those will target
splitting up the config sequences and 5G-QSGMII is special there.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Rename the function that currently "applies patches" so that it covers
everything it does (and will do). It doesn't only apply patches but in
general performs configuration of a SerDes for a particular hardware
mode.
While at it, remove a print above that call because it is both placed
wrong and redundant due to what the generic pcs_config prints.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Change how patches are applied to reduce redundancy and make the code
more readable. Define a generic function that applies any patch. Within
the RTL930x patch application, define a local macro that helps to get
rid of repeated even/odd checks. While making the code cleaner, it is
also a preparation for further refactoring here.
This adds a local helper macro intended to be only temporary but keeps
the style of the code clean by avoiding a lot of if-else clauses.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/22582
Signed-off-by: Robert Marko <robimarko@gmail.com>
Several devices (including the upcoming DGS-1250) need a fully
featured port definition that includes:
- port number
- label
- led-set
- pcs-handle
- phy-handle
- phy-mode
Provide a new macro for that and make the Zyxel XGS-1210 series
the first consumer of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22591
Signed-off-by: Robert Marko <robimarko@gmail.com>
In the blamed commit, the wrong partition name for ART was used.
It was later discovered that the partition table uses "0:ART" instead of
"art" for the ART partition name thus breaking caldata extraction.
So, fix the partition name.
Fixes: ee5999cf78 ("treewide: linksys: use nvmem MAC for hw_mac_addr")
Signed-off-by: Anthony Sepa <protectivedad@gmail.com>
Signed-off-by: Robert Marko <robimarko@gmail.com>
