The TP-Link TL-ST1008F is an 8-port multi-gig switch with 8x SFP+ ports
which support 1G/2.5G/10G speeds. Out of the box it is an unmanaged
switch but with RTL9303 and sufficient RAM + Flash it easily can run as
a managed Linux switch.
Hardware:
- Realtek RTL9303 Switch SoC
- Winbond 25Q256JVFQ (32MB flash)
- Samsung K4B4G1646E-BYMA (512MB DDR3 SDRAM)
- TCA9534 GPIO extender to control the port LEDs
- 8x SFP+ 1/2.5/10G slot
- Serial: 3V3 logic, 115200 8N1
- 5-pin JTAG
- physical tri-state switch (used by stock firmware for port speed
config)
- 24-LED port speed matrix
- robust full-metal case
Power is supplied via a 12V 2A standard barrel connector.
There are THT holes on the PCB for serial console next to the flash chip
and JTAG pads. Serial uses 3V3 logic and standard 115200-8N1 config.
Pinout is labeled on the PCB.
All ports/connectors and LEDs are on the back, only Power LED is on the
front.
Hints before flashing
----------------------
* It is recommended to backup the stock flash contents before proceeding.
Backup can be done from U-Boot (with memory display), from OpenWrt
initramfs or probably with SPI flash programmer.
There is no stock recovery functionality.
* Use a small image for RAM boot or first flash. Since you need to use
ymodem, this is really slow and takes time.
* This does not keep the dual-partition layout for firmware to have more
space available for a single OpenWrt installation.
Initial flashing
----------------------
The stock U-boot has broken networking thus no TFTP available. Serial
transfer only.
1. Open device and connect serial as per layout and settings
(recommended to use picocom, ymodem not working with minicom)
2. Connect power to device and press Esc when prompted to enter
the U-Boot console.
3. Boot initramfs
* in the U-Boot console:
loady 0x82000000 (load OpenWrt image via ymodem)
CTRL-A CTRL-S <initramfs.bin> (specify initramfs image for
picocom to upload)
bootm 0x82000000 (boot initramfs from RAM)
(Just to be on the safe side, backup your flash now while RAM-booted)
4. Connect network to your device
5. Upload the sysupgrade image (e.g. with scp)
6. Do sysupgrade
There's no need to adjust the bootcmd in U-Boot. Networking is running
fine once the realtek driver initialized everything in OpenWrt. No
functional difference with running 'rtk network on' within U-Boot
before. Running this even fails and returns with an error.
Return to stock
------------------
This only works if you did a backup of the flash before flashing
OpenWrt. Stock dump then can be flashed from within U-Boot or OpenWrt.
There is no vendor firmware image because this is an unmanaged switch!
CAUTION: Make sure to not overwrite the U-Boot partition(s). If you do
not have a flash programmer, you may not be able to debrick
your device then.
Co-authored-by: Balázs Triszka <balika011@gmail.com>
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Only 2 devices use leading zeroes to pad interface names,
align the remaining ones so that it is consistent.
Signed-off-by: Joe Holden <jwh@zorins.us>
Link: https://github.com/openwrt/openwrt/pull/18913
Signed-off-by: Robert Marko <robimarko@gmail.com>
Three different code paths for the same phy model. Now the bus
is prepared to handle c45 (mmd) read/writes correctly. Remove
the custom implementations and let generic kernel functions do
their best. To achieve this
- disable the PHY-mode EEE in rtl821x_config_init() as upstream does
- provide mmd read/write functions that avoid EEE via c45 over c22
While chaning the phy_driver functions sort them alphabetically.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
rtl8214fc_media_is_fibre() will need to be run when bus lock is held.
Split the function into two versions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
As the mdio bus has been hardened and can now handle c45 requests
the DSA driver must honor that as well. For this
- add proper upstreamed bus read_c45 and write_c45 functions
- take over the disabled port mask from upstream bus
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
With the follow up EEE patches the mdio bus will run c22 and c45
accesses during initial scan. Especially when accessing addresses
beyond the CPU port phy requests might fail in a way that cannot
be handled gratefully. Do two things
- do not allow access to addresses starting from cpu port
- set the scan disable bitmask to ports starting from cpu port
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some bits where missed during the last enhancement of the mdio
patch. In the forthcoming patches the phy_mask will be populated
to avoid unwanted ports (>= cpu port) from being scanned. Add
additional locations where 32 bit values need to be converted
to 64 bits.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
If mmd and normal phy ops are issued the bus is lost because
of wrong park page settings. Force it to 0x1f as in GPL.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Allow to build the new kernel.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
The new kernel has relocated the definition of struct platform_device.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
The DSA driver uses set_mac_eee() for the outside API while
the interal helper is called port_eee_set(). Align that.
Additionally do not call the internal helpers directly by
the function names but use the register assignments.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Upstream will get rid of the get_mac_eee() function in the DSA
driver and replace it by a boolean alternative. While we fill a
lot of data here (because of EEE bugs in the Realtek phy layer)
other DSA drivers only return if EEE is available or not for a
port. To make the next kernel upgrade easier follow that design.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
To avoid unneeded interrupts the R4K timer is deactivated during
secondary cpu initialization. This is currently done during
phase init_secondary(). With the upgrade to 6.12 the kernel runs
a primary/secondary cpu timer/counter synchronization to verify the
proper setup in synchronise_count_slave(). That runs at a later
point in time and expects the secondary counter to be fully
functional. Finding a deactivated counter results in the following
messages:
WARNING: CPU: 1 PID: 0 at arch/mips/kernel/sync-r4k.c:99 check_counter_warp+0x220/0x254
Warning: zero counter calibration delta: 0 [max: 6500000]
Counter synchronization [CPU#0 -> CPU#1]:
Measured 278760029 cycles counter warp between CPUs
Relocate the deactivation to smp_finsh() at the end of the cpu
startup sequence. Additionally polish the startup code and remove
all unneeded parts.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Per IEEE 802.3 definition we have:
- parallel XGMII for single 10GBit ONLY links
- serial USGMII for 8 port 1GBit links (not known by kernel)
- serial USXGMII: for single/multiple links with a total bandwidth of 10GBit
The phy-mode of the first eight ports of the XGS1250-12 have always been
defined as XGMII (without S). This came from a confusion with the similar
named Realtek proprietary XSGMII (with S) mode that is basically 10GB SGMII.
From the above definition this is wrong but worked until kernel 6.6. With
the upgrade to 6.12 there is an enforced capabilities check within
phy_caps_from_interface() and link validation fails with
lan1: validation of xgmii with support 62ef and advertisement 62c0 failed: -EINVAL
lan1: failed to connect to PHY: -EINVAL
lan1: error -22 setting up PHY for tree 0, switch 0, port 0
Switch the ports to USXGMII as the most flexible option. This might be no
final solution but at least it better describes the phy/mac link.
Fixes 5b8b382df9 ("realtek: Add support for ZxXEL XGS1250-12 Switch")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Fix minor compilation errors due to kernel changes.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Upstream has integrated the Realtek target into the generic MIPS
initialization and so MACH_REALTEK_RTL has gained some new features.
Especially:
- CONFIG_MACH_GENERIC_CORE generates central modules
- board-realtek module adds device specific extensions
The current downstream initialization works well and upgrading to
kernel 6.12 is not the right time to harmonize this. Modify the
MACH definitions to the current needs.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
The validate function no longer exists in phylink_mac_ops. Remove
it for the internal ethernet interface. Instead provide some
meaningful mac capabilities.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Not only the link but also the mac capabilities are needed here.
Additionally do some alphabetical sorting.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
The old upstream notation has been changed to something not so racist.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
EEE functions are now called with ethtool_keee instead of
ethtool_eee. Replace all occurrences. This will fix function
signature checks but still produces compilation errors due
to structure changes.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Patches where fuzz had to be cleaned up.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
All these patches needed no manual intervention and applied cleanly
with new source code positions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Thanks to Chris Packham this driver got upstreamed. Drop the
downstream files and patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Automatically generated commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Automatically generated commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Automatically generated commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Automatically generated commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Automatically generated commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
Automatically generated commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18935
Signed-off-by: Robert Marko <robimarko@gmail.com>
* Extends SoC thermal sensor on rtl839x
* Tested on HP JG928A
Signed-off-by: Stephen Howell <howels@allthatwemight.be>
Link: https://github.com/openwrt/openwrt/pull/18825
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add support for V3 of the Engenius EWS2910P PoE switch. Like its v1
brother, This is an RTL8380 based switch with two SFP slots, and PoE
802.3af one every RJ-45 port.
Unlike its older brother, the max budget is 55W instead of 61.6 W.
Investigation into the communication protocol with the PoE controller
is ongoing, though it appears the vendor firmware configures the PSE
with a per-port budget of 30.0W.
Specifications:
---------------
* SoC: Realtek RTL8380M
* Flash: 32 MiB SPI flash Macronix MX25L25635E
* RAM: 256 MiB (As reported by bootloader)
* Ethernet: 8x 10/100/1000 Mbps with PoE
2x SFP slots
* Buttons: 1 "Reset" button on front panel
1 "LED mode: button on front panel
1 "On/Off" Toggle switch on the back
* Power: 48V-54V DC barrel jack
* UART: 1 serial header (JP1) with populated 2.54mm pitch header
Labeled GRTV for ground, rx, tx, and 3.3V respectively
* PoE: 1 STM ST32... microcontroller (U15)
1 RTL8238B PSE controller
Works:
------
- (8) RJ-45 ethernet ports
- Switch functions
- LEDs and buttons
Not yet enabled:
----------------
- Power-over-Ethernet (requires realtek-poe support for RTL8232B)
Install via web interface:
-------------------------
The factory firmware will accept and flash the initramfs image. It is
recommended to flash to "Partition 0". Flashing to "Partition 1" is
not supported at this point.
The factory web GUI will show the following warning:
" Warning: The firmware version is v0.00.00-c0.0.00
The firmware image you are uploading is older than the current
firmware of the switch. The device will reset back to default
settings. Are you sure you want to proceed?"
This is expected when flashing OpenWrt. After the initramfs image
boots, flash the -sysupgrade using either the commandline or LuCI.
Install via serial console/tftp:
--------------------------------
See commit 2cfaab4549 ("realtek: add support for EnGenius EWS2910P").
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15217
Signed-off-by: Robert Marko <robimarko@gmail.com>
When the Engenius EWS-2910P was added, only v1 was known. Move the
common parts to a dtsi, and split up the support to acccount for the
hardware version.
On v3, for example, the root partition uses a different uImage magic.
Add a "engenius,ews2910p-v1" compatible, while leaving the legacy
"engenius,ews2910p" to also mean v1.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15217
Signed-off-by: Robert Marko <robimarko@gmail.com>
DSA silently drops internal phy access to ports >= 32 in dsa_user_phy_read()
and dsa_user_phy_write(). The code shows:
static int dsa_user_phy_read(struct mii_bus *bus, int addr, int reg)
{
struct dsa_switch *ds = bus->priv;
if (ds->phys_mii_mask & (1 << addr))
return ds->ops->phy_read(ds, addr, reg);
return 0xffff;
}
With ds->phys_mii_mask being a 32 bit variable the reason is clear. So do
not only increase the max values but also adapt the needed bitmasks in
the dsa and phy code. This fixes the dsa_user_ports() and dsa_cpu_ports()
too.
While we are here combine the old separated patches because dsa, mdio and
phy are tigthly coupled.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18846
Signed-off-by: Robert Marko <robimarko@gmail.com>
In 2023 upstream has tightened compiler checks with this patch
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit
/scripts/Makefile.extrawarn?h=v6.15&id=0fcb70851fbfea1776ae62f67c503fef8f0292b9
A consistent function definition is now needed. I.e.
- functions must be either declared with "static" or
- functions need an additional declaration (in the header file)
Before upgrading the Realtek target to 6.12 clean the code so that the main
6.12 PR can focus on real issues from the version bump.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18925
Signed-off-by: Robert Marko <robimarko@gmail.com>
In 2023 upstream has tightened compiler checks with this patch
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit
/scripts/Makefile.extrawarn?h=v6.15&id=0fcb70851fbfea1776ae62f67c503fef8f0292b9
A consistent function definition is now needed. I.e.
- functions must be either declared with "static" or
- functions need an additional declaration (in the header file)
Before upgrading the Realtek target to 6.12 clean the code so that the main
6.12 PR can focus on real issues from the version bump.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18925
Signed-off-by: Robert Marko <robimarko@gmail.com>
In 2023 upstream has tightened compiler checks with this patch
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit
/scripts/Makefile.extrawarn?h=v6.15&id=0fcb70851fbfea1776ae62f67c503fef8f0292b9
A consistent function definition is now needed. I.e.
- functions must be either declared with "static" or
- functions need an additional declaration (in the header file)
Before upgrading the Realtek target to 6.12 clean the code so that the main
6.12 PR can focus on real issues from the version bump.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18925
Signed-off-by: Robert Marko <robimarko@gmail.com>
In 2023 upstream has tightened compiler checks with this patch
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit
/scripts/Makefile.extrawarn?h=v6.15&id=0fcb70851fbfea1776ae62f67c503fef8f0292b9
A consistent function definition is now needed. I.e.
- functions must be either declared with "static" or
- functions need an additional declaration (in the header file)
Before upgrading the Realtek target to 6.12 clean the code so that the main
6.12 PR can focus on real issues from the version bump.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18925
Signed-off-by: Robert Marko <robimarko@gmail.com>
In 2023 upstream has tightened compiler checks with this patch
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit
/scripts/Makefile.extrawarn?h=v6.15&id=0fcb70851fbfea1776ae62f67c503fef8f0292b9
A consistent function definition is now needed. I.e.
- functions must be either declared with "static" or
- functions need an additional declaration (in the header file)
Before upgrading the Realtek target to 6.12 clean the code so that the main
6.12 PR can focus on real issues from the version bump.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18925
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are still a lot of mdio functions scattered around the code.
Move the RTL838x serdes helpers closer to the bus, add the proper
prefix and simplify the functions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18847
Signed-off-by: Robert Marko <robimarko@gmail.com>
There is a patch/bug cascade in the realtek target phy code that must be resolved.
1. The phy_driver structure is patched to add features ONLY needed for RTL8214FC
2. The kernel is patched to allow switching fiber/copper port of phys through ethtool
by calling these new features.
3. With those patches applied the bootup always switches RTL8214FC ports to copper.
Even if a SFP module was found before and the phy driver switched to fibre before.
3. So another patch is needed that reprobes the SFP module to activate fiber again.
4. Because of the reprobing we need a fourth patch that avoid duplicate devices.
Simplify this by removing all patches and reusing the existing ethtool phy tunable
interface. The command line usage might be counterintuitive but it avoids tons of
problems in the code. In addition, this scenario is not used frequently.
Before:ethtool -s lan25 port fibre/tp
After: ethtool --set-phy-tunable lan25 downshift on/off
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18816
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MIPS CPC (Cluster Power Controller) is setup during boot and can take
its configuration from the devicetree. This is currently not possible
because the cpc probing happens before dt initialization. Call order
during startup is:
setup_arch()
prom_init() <- our function
mips_cpc_probe()
smp_stuff()
arch_mem_init()
device_tree_init() <- our function
unflatten_and_copy_device_tree()
To avoid ugly hacking and support a clean devicetree relocate the cps/smp
stuff to device_tree_init(). This is basically the same location as in
generic mips initialization.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Link: https://github.com/openwrt/openwrt/pull/18888
Signed-off-by: Robert Marko <robimarko@gmail.com>
Make it easier to upgrade the kernel in the future. For this remove
the 320-harden-fw_init_cmdline.patch and add the logic into the
startup sequence at the right place.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18853
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL931x devices are dual core with two threads each. That is a total
of 4 VPEs (CPUs) in the kernel. Adapt the kernel config for that.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Link: https://github.com/openwrt/openwrt/pull/18889
Signed-off-by: Robert Marko <robimarko@gmail.com>
Since the early beginning of the Realtek DSA driver there is an uncovered
locking issue between the standard (parent) mdio bus and the DSA (child)
mdio bus. This comes from the fact that the DSA bus simply links to the
parent read and write functions and calls them directly. This leads to
the following lock issue.
- Child bus calls phy_read/write functions and uses its internal lock
- Parent bus calls phy_read/write functions and uses its internal lock
It becomes clear that critical section can be accessed twice without
knowing that a operation from the other bus is currently active. This
can lead to critical malfunctions because the mdio driver needs a lot of
internal magic to get page selection done right. Effects are:
- The original page is lost after a phy_write/read_paged() call
- dmesg like "Realtek RTL8218B (external) rtl838x slave mii-0:00:
Expected external RTL8218B, found PHY-ID 6b23"
Other DSA drivers simply use the read/write functions from the parent bus
and thus avoid locking issues. Do it the same way.
Fixes: 2b88563ee5 ("realtek: update the tree to the latest refactored version")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18824
Signed-off-by: Robert Marko <robimarko@gmail.com>
There are currently two power functions for the RTL8214FC in the driver
- rtl8380_rtl8214fc_on_off(): powers on/off both ports
- rtl8214fc_power_set(): powers on/off fibre or copper individually
While it seems obvious to merge these, one of them uses extended register
29 and the other register 30 to achieve the update. From looking at the
GPL source drops both methods exist with exactly the same operations. So
where to go from here? The descision was made based on:
- register 30 is only used during patching, 29 during normal operation
- Avoid raw page if possible to use function for RTL839x
So the attached patch was created. The result in the power down bits
was compared for the two old and the new implementation. Result is
always the same.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18707
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL9311 switches (like the Linksys LGS352C) will boot but have not set
the right family id in the soc_info structure. Fix that so drivers do
their work right when checking for that.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18871
Signed-off-by: Robert Marko <robimarko@gmail.com>
Cleanup the code of the RTL83xx packet receive interrupt handler. Not
only for better readability but to avoid inconsistencies and stalls on
the RTL839x targets.
The current implementation seems to come from the GPL source code.
Calling the existing cleanup() function inside the interrupt context
without any locks conflicts with SMP & NAPI polling and makes things
worse instead of giving any benefit. Simply ignore RX buffer overruns
and let the device handle packet dropping itself.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18855
Signed-off-by: Robert Marko <robimarko@gmail.com>
RFC4541, section 2.1.2 says:
Packets with a destination IP (DIP) address in the 224.0.0.X range
which are not IGMP must be forwarded on all ports.
And section 3 says:
In IPv6, the data forwarding rules are more straight forward because
MLD is mandated for addresses with scope 2 (link-scope) or greater.
The only exception is the address FF02::1 which is the all hosts
link-scope address for which MLD messages are never sent. Packets
with the all hosts link-scope address should be forwarded on all
ports.
However, currently when a listener on FF12::1 or FF12:🔢0:1 for
example joins then not only packets to these addresses but also for
FF02::1 won't be flooded to all ports anymore, too. Which violates
RFC4541.
This happens because A): They all map to the same ethernet multicast
address, that is 33:33:00:00:00:01. And B) the VLAN profile L2
unknown MC flood setting will only apply flooding of 33:33:00:00:00:01
if there is no specific listener registered for it.
So to fix this, avoid registering an MDB entry in the switch for
33:33:00:00:00:01 at all.
The downside of this is that FF12::1, FF12:🔢0:1 etc.
will always be flooded, too. However fixing the handling of 224.0.0.X
and FF02::1 and adhering to RFC4541 must have priority to avoid
undesired packetloss, to avoid breaking IPv4/IPv6.
Tested-on: ZyXEL GS1900-24HP v1
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Linus Lüssing <linus.luessing@c0d3.blue>
Link: https://github.com/openwrt/openwrt/pull/18769
Signed-off-by: Robert Marko <robimarko@gmail.com>
Kernel does
if (phydev->drv->set_loopback)
ret = phydev->drv->set_loopback(phydev, enable, speed);
else
ret = genphy_loopback(phydev, enable, speed);
So no need to explicitly set genphy_loopback() in phy_driver. Drop
references to let kernel do its work.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18782
Signed-off-by: Robert Marko <robimarko@gmail.com>
We are lucky to have a working realtek environment. But some things where mixed
heavily. To say it clear a bus is a bus and an ethernet is an ethernet. With
the new naming conventions and defines this becomes even more obvious.
Decouple it by moving the bus specific parts out of the ethernet device. To
make the code more readable rename bus_priv variables to priv and sort variable
definitions in inverse tree order (length descending) where it makes sense.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18402
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
At least since 2022 there is a major bug in the MDIO driver that
produces out-of-bound reads and erratic behaviour during initialization.
- mdiobus_scan_bus_c22() scans the bus for 64 devices (PHY_MAX_ADDR)
- private bus structure only supports 57 entry arrays (MAX_PORTS)
All the bus/reader writer functions accept calls with addr>=57 and will
silently read beyond their limits. This can lead to ghost SERDES like
https://github.com/openwrt/openwrt/issues/18665#issuecomment-2846053813
Add proper boundary checks and end the functions with -ENODEV that is
the only accepted error code from the bus scan function.
Fixes: 0536c582e6 ("realtek: Fix RTL931X Ethernet driver") etc ...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18402
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
These two arrays have been fixed to some sane size (= 64 ports). Now
that everything is in place reuse the global RTMDIO_MAX_PORT define.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18402
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Relocate the bus structure definition into the MDIO source code area
of the ethernet driver. So if the real bus driver is forked from the
rest of the code only one area needs to be removed. Rename it to make
clear it belongs to the bus.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18402
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Although a dfine is used to set the maxiumum number of SMI
busses (=4) it is not used at all appropriate places in the code.
Replace hard coded constants with that define.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18402
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Inside the ethernet driver lives the mdio bus. It is not always clear
what belongs where. Prefix some leftovers from the kernel 6.6 refactor
to clearly state what belongs to the bus. Group all defines together
in one place. This commit has no functional changes.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18402
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
There are no supported devices on this sub-target. It can be
considered that it is still under development. Therefore,
there is no need to make the buildbot build it every day.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18757
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL8214FC currently uses generic PHY functions. That makes it look like a copper
device. Switching to/from fibre works fortunately but the autonegotiation handling
still works on MII_LPA (PHY register 5) as if a copper link is used. Fix that by
- advertising a superset of TP/FIBRE features
- using clause 37 functions when on fibre
Additionally enhance the code of the driver to assist further development.
- log the speed of the inserted module to detect wrongly inserted 10gbase-r modules
- order phy driver functions alphabetically (keep match/name on top)
- remove genphy_loopback as the kernel uses it if not provided
Remark! The driver internally uses PORT_MII for the TP port. Align with that and
report MII to ethtool instead of TP. Other drivers do the same and it can be
changed in the future if needed.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18724
Signed-off-by: Robert Marko <robimarko@gmail.com>
When many multicast entries are installed broadcast flooding might
potentially stop working for several ports. This is because the layer
2 broadcast flood port mask index has the wrong offset. It should be
9 bits, matching the 2^9 = 512 indexes on rtl838x, not 12.
The wrong offset leads to L2_BC_FLD_PMSK being set to 504, not 511
((511 << 12) >> 9) & 511 = 504). So, as by default an unset PMSK
is set to all ports, the issue would only become noticeable once
many multicast entries are installed, causing the 504th entry to be set
to something other than all ports.
Fixing this by setting the offset to 9 bits, to correctly point to our
511th reserved entry for all ports.
Tested-on: ZyXEL GS1900-24HP v1
Fixes: 28e972b2ea ("realtek: Configure initial L2 learning setup")
Signed-off-by: Linus Lüssing <linus.luessing@c0d3.blue>
Link: https://github.com/openwrt/openwrt/pull/18733
Signed-off-by: Robert Marko <robimarko@gmail.com>
Some DTS files have a qsgmii link mode for the CPU port. This does
not harm but it is wrong. The CPU port of the realtek switch is always
directly connected to the switch by some unknown wiring and should
therefore be described as internal. Align the wrongly defined DTS
files to the standard.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18691
Signed-off-by: Robert Marko <robimarko@gmail.com>
Commit d7e82c78d7 added a generic kernel patch that exposes a new
symbol REALTEK_PHY_HWMON when REALTEK_PHY and HWMON are enabled. The new
symbol was added to kmod-phy-realtek, but the kmod is not used in the
realtek target.
Fixes: d7e82c78d7 ("generic: backport Realtek PHY patches from upstream")
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Probing of the RTL8214FC on RTL839x is currently very strange.
- On RTL8393 nothing is detected and only generic PHY is reported
- On RTL8392 the port 1 is not detected while port 2-4 seem to work
Someone left a special RTL8393 detection rules that seems to indicate
that the we probe the internal SerDes instead. That is not true. Since
upgrade to kernel 6.6 the RTL8218/RTL8214FC detection is 100% accurate
and probing functions are only called when really needed.
Fix the issue by removing the condition. For now do PHY patching only
on the RTL838x where it already worked before.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/18671
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
The ATS SFP GT-T quirk patch was backported to stable kernel 6.6 but
was not notice while bumping the kernel version as they listed the quirk
at the bottom of the SFP quirk table while our hack patch put it at the
top.
With migrating to the upstream version, the duplication was made more
apparent.
Drop the double entry for the SFP module as it's already there and not
needed and refresh patches.
Link: https://github.com/openwrt/openwrt/pull/18484
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Move all patch that got merged upstream from pending to backport and add
related tag. This is to make it easier to update to kernel 6.12.
Patch 680 required some special care as the upstream version had to be
split in a series of 6 patch.
Referesh all affected patch.
Link: https://github.com/openwrt/openwrt/pull/18464
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This patch adds support for D-Link DGS-1210-26 rev. F1
Hardware specification
----------------------
* RTL8382M SoC, 1 MIPS 4KEc core @ 500MHz
* 128MB DRAM
* 32MB NOR Flash (MX25L25635E)
* 24 x 10/100/1000BASE-T ports
* 2 x SFP ports
* Power LED
* Reset button on front panel
Installation using OEM webinterface
-----------------------------------
1. Make sure you are running OEM firmware from secondary slot. If not, switch to image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image squashfs-factory_image1.bin via Tools > Backup / Upgrade Firmware > image1
3. Toggle startup image via System > Firmware Information > Boot from image1
4. Tools > reboot
Known working firmware version for this procedure: 6.20.007
Installation using TFTP and serial console
------------------------------------------
1. Prepare a TFTP server with the OpenWrt *initramfs-kernel.bin and assign it an IP from 10.90.90.0/24 (except 10.90.90.90)
2. Connect the TFTP server to one of switch's ports
3. Connect to the serial console (115200 baud) and power on the switch
4. Press the ESC key once you see "Hit Esc key to stop autoboot" in the console output
5. Press CTRL+C keys to get into the real U-Boot prompt
6. Init the network with the command "rtk network on"
7. Load the OpenWrt image with the command "tftpboot 0x8f000000 <TFTP_SERVER_IP>:<IMAGE_FILE>"
(<TFTP_SERVER_IP> is the TFTP server's IP, e.g. 10.90.90.100; <IMAGE_FILE> is the name of the image provided by the TFTP server)
8. Boot the OpenWrt image with the command "bootm"
9. Browse to https://192.168.1.1/cgi-bin/luci/admin/system/flash
10. Upload the the OpenWrt *squashfs-sysupgrade.bin to the switch
11. Wait for it to reboot
Signed-off-by: Christian Steiner <christian.steiner@outlook.de>
Link: https://github.com/openwrt/openwrt/pull/18378
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Currently, network ports using PHYs get a link, but there is no traffic.
Make it work again by moving the MAC config to phylink_mac_link_up.
A similiar change has been previously applied for RTL83xx in commit
cd958d945b ("realtek: 6.6: refactor mac config and link up for
RTL83xx").
Fixes: https://github.com/openwrt/openwrt/issues/17010
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Tested-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18268
Signed-off-by: Sander Vanheule <sander@svanheule.net>
RTL8261N is used on some Airoha and Realtek devices. Move the driver
from Mediatek to generic so it can be used everywhere.
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18163
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The CONFIG_NET_SWITCHDEV option is needed by CONFIG_DSA and some other
options. It is boolean, we have to compile it into the kernel it self.
Activate it for all targets in the generic configuration, it is already
activated for most of them. This allows to install DSA drivers as a
module.
On the ramips/mt7620 target the kernel would grown by 4.5kB.
For some small targets which do not support a DSA switch by default the
option is deactivated.
Link: https://github.com/openwrt/openwrt/pull/17668
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This fixes the handling of some FS copper SFP modules using the RollBall
protocol and needing some extra treatment.
Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Some devices have both the color/function and label property defined.
The label can be constructed from the former properties, making it
redundant.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This makes sgmii work for 1000Base-T SFPs by stupidly adding the sgmii mode
wherever 1000base-x is accepted. No intelligence has been used in the
process. But it "works for me".
There is an obvious need for refactoring this code to make it more obvious
how and why we configure the mac/phy link like we do for different modes.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
These features have been added to the mdio-i2c driver and are now used by
the sfp driver. The support is required for some newer SFPs.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This driver use "phy-handle" as a placeholder for mac configuration
data. Such handles are therefore required for all ports - even those
connected directly to SFP slots and having a managed property set to
"in-band-status".
The DSA core will register these nodes as if they are real phys. This
prevents later attachment of pluggable phys with errors like
sfp sfp-p8: sfp_add_phy failed: -EBUSY
Replace the virtual SFP slot handles with "pseudo-phy-handle" to keep
the driver logic as-is but hide the node from the DSA core.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The SMBus patch broke the logic and caused the driver to always
register an mdio bus, regardless of the sfp. Restore original
logic.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Re-probing on interface up will register a new duplicate hwmon device. Skip
the hwmon probe if we already have a sensor device.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Fix a typo which resulted in wrong .read hooks and unset .write
hooks. This made I2C_SMBUS_BLOCK_DATA transfers dereference the
NULL .write hook and Oops.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The log noise emmitted by this driver is overwhelming, even for developers
looking at specific issues. Demoting to debug allows individual messages
to be dynamically enabled instead.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Adding a static IPv4 route made the driver repeatedly print
rtl83xx_l3_nexthop_update: Setting up fwding: ip 192.168.1.42, GW mac 0000001b21a7xxxx
Route with id 3 to 192.168.99.0 / 24
rtl83xx_l3_nexthop_update: total packets: 0
Warning: TEMPLATE_FIELD_RANGE_CHK: not configured
These messages are only useful to developers while debugging offloading.
Demote to debug level, which in general is more useful for developers
by allowing precise dynamic control.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/17950
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Both hardware and firmware of these devices appears identical except for the
manufacturers logo and device name. The documented XikeStor SKS8300-8X
installation method is verified to work on the ONTi ONT-S508CL-8S using
Openwrt images made for the XikeStor SKS8300-8X. This includes the OEM boot
loader magic password phrases.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/18071
Signed-off-by: Sander Vanheule <sander@svanheule.net>
By switching to the new RTL8231 driver in commit b7af54d5c1 ("realtek:
Simple conversions to RTL8231 MFD driver"), the bootloader state of the
RTL8231's pins is now maintained. As the bootloader de-asserts the PoE
enable signal, this means PoE output is no longer available.
Add a gpio-hog with high output, restoring the line value from when the
pin was configured (by default) as an input with a pull-up resistor.
This will hard-enable the PoE output, but the individual ports can still
be administratively disabled by realtek-poe or a similar tool.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The JG928A has an RTL8231 on the aux mdio bus. Add it to dts to expose
the GPIO pins used to control and monitor the fan speed. To enable speed
control, add the appropriate kernel driver module to DEVICE_PACKAGES.
Of note, this does not control all fans for the unit. The power supply
fans are not controlled.
Signed-off-by: Evan Jobling <evan@jobling.au>
Link: https://github.com/openwrt/openwrt/pull/17699
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The old RTL8231 driver integrated the MDIO bus access with the GPIO
control ops, making this driver not very portable to newer platforms.
It depended on the SoC ID instead of the compatible to determine the
MDIO access register, further complicating portability.
A new MFD driver is now available, which offers proper pin config as
well as optional LED support, which can work on any (bitbanged) MDIO
bus. Now that all devices have been migrated, we can drop the old code.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
By switching to the new RTL8231 driver in commit b7af54d5c1 ("realtek:
Simple conversions to RTL8231 MFD driver"), the bootloader state of the
RTL8231's pins is now maintained. As the bootloader de-asserts the PoE
enable signal, this means PoE output is no longer available.
Add a gpio-hog with high output, restoring the line value from when the
pin was configured (by default) as an input with a pull-up resistor.
This will hard-enable the PoE output, but the individual ports can still
be administratively disabled by realtek-poe or a similar tool.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Switch the implementation for the RTL8231 GPIO expander to the new
driver.
This allows specifying the GPIO driving the RTL8231's reset as a proper
MDIO reset line, so the gpio-hog can be dropped. Since it was pinned at
a high level, the reset line is actually active-low (i.e. high when not
in reset).
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the common external GPIO DTSI file for the DGS-1210 devices to
use an MDIO device on the auxilairy MDIO bus, as the original driver was
doing behind the screen.
Switching to the new driver will allow for full pin-control and will no
longer reset pin config set by the bootloader.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DTS file for the DGS-1210-10P is slightly different from the other
DGS-1210 devices, in that it didn't specify a gpio-restart node when it
was added. The gpio-restart has been found to work on the DGS-1210-10P
as well, so switch it over to the common definitions.
This converts the last device from the product family to the common
definition for the (external) GPIOs.
Tested-by: Michel Thill <jmthill@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The 'indirect-access-id' property on gpio0 is a remnant from the
original GPIO driver. This property has not been relevant on the SoC's
embedded GPIO controller for a long time, so just drop it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Change devices with RTL8231 GPIO expander definition that can easily be
translated to the new RTL8231 binding and carry over any gpio-hogs. This
will let them use the new RTL8231 MFD driver, without any functional
changes.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Zyxel GS1900-8 v2 devices have been produced more recently than v1
devices. As there are v1 boards with RTL8380M rev. C SoCs, it can likely
safely be assumed that all v2 devices will also have a recent SoC
revision, supporting the hardware auxiliary MDIO controller.
Make the GS1900-8 v1 use an emulated auxiliary MDIO bus, for backward
compatibility with devices containing an RTL8380M rev. A.
Since the devicetrees are otherwise identical, GS1900-8 v1 devices with
an RTL8380M rev. B or C will also be able to use the (more efficient) v2
image. This includes any currently functioning device with OpenWrt, so
include the old compatible as a supported device for the GS1900-8 v2.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The mdio-gpio driver is required to support early revision of RTL8380M
slicon (rev A) where the auxilairy MDIO controller does not function
correctly. Add this driver to the rtl838x kernel so devices with old
SoCs are also able to function correctly.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
In order to be able to define the external GPIO controller on an
emulated MDIO bus, move the controller definition outside of the main
GS1900 include for RTL838x-based devices.
Additionally, a new DTSI is provided defining the RTL8231 on the
emulated MDIO bus.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Some RTL8380M-based devices have been around for a long time and use an
early A revision of the RTL8380M SoC. This revision has an issue with
the auxiliary MDIO controller, causing it to malfunction. This may lead
to device reboots when the controller is used.
Provide a bit-banged MDIO bus, which muxes the auxiliary MDIO pins to
their GPIO function. Although this will result in lower performance,
there should otherwise be no functional differences.
Link: https://github.com/openwrt/openwrt/issues/9534
Signed-off-by: Sander Vanheule <sander@svanheule.net>
As the bootloader is reconfiguring the RTL8231 on these devices anyway,
no pin state can be maintained over warm reboots. This results in for
example the PoE disable pin always being asserted by the bootloader.
Define the GPIO line linked to the RTL8231's reset so the MDIO subsystem
will also reset the expander on boot and ensure the line in the correct
state.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Supported devices are listed in the metadata as the first part of the
DTS compatible. This normally follows the format "vendor,device".
When updating the device name of the 180W 1920-8G PoE an underscore was
used, instead of a comma, to join the vendor and device name. This will
lead to warnings for users wanting to sysupgrade a device with an older
compatible, as the device's info does not match the one the metadata.
Fixes: 987c96e889 ("realtek: rename hpe,1920-8g-poe to match hardware")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
XikeStor (Seeker) SKS8300-8X is a 8 ports Multi-Gig switch, based on
RTL9303.
Specification:
- SoC : Realtek RTL9303
- RAM : DDR3 512 MiB
- Flash : SPI-NOR 32 MiB (Winbond W25Q256JVFIQ)
- Ethernet : 8x 1/2.5/10 Gbps (SFP+)
- LEDs/Keys (GPIO): 1x/1x
- UART : "Console" port on the front panel
- type : RS-232C
- connector : RJ-45
- settings : 9600n8
- Watchdog : Diodes PT7A7514WE
- Power : 12 VDC, 2 A
Flash instruction using initramfs image:
1. Prepare TFTP server with an IP address "192.168.2.36"
2. Connect your PC to Port1 on SKS8300-8X
3. Power on SKS8300-8X and interrupt by Ctrl + B
4. Login to the vendor CLI by Ctrl + F and "diagshell_unipoe_env"
5. Login to the U-Boot CLI by "debug_unish_env" command
6. Enable Port1 with the following commands
rtk 10g 0 fiber1g (or fiber10g if 10GBase-*R)
rtk ext-devInit 0
rtk ext-pinSet 2 0
Note: the last command sets tx-disable to low
7. Download initramfs image from TFTP server
tftpboot 0x82000000 <image name>
8. Boot with the downloaded image
bootm
9. On the initramfs image, backup the stock firmware if needed
10. Upload (or download) sysupgrade image to the device
11. Erase "firmware" partition to cleanup JFFS2 of stock FW
mtd erase firmware
12. Perform sysupgrade with the sysupgrade image
13. Wait ~120 sec to complete flashing
Notes:
- A kernel binary "nos.img" needs to be stored into JFFS2 filesystem
using 4KiB erase block instead of 64KiB.
- PT7A7514WE is handled by hardware-assited system LED output
(blinking).
- Some Japanese users asked to XikeStor about maximum power limit of
SFP+ ports and got approximate criteria:
- per port : <= 2.9 W
- total (8 ports): <= 15.8 W
MAC addresses:
eth0 : 84:E5:D8:xx:xx:37 (board-info (stock:"flash_raw"), 0x218 (hex))
(ports): 84:E5:D8:xx:xx:36 (board-info (stock:"flash_raw"), 0x1f1 (hex))
Reverting to stock firmware:
1. Prepare OpenWrt SDK to use the mkfs.jffs2 tool contained in it
Note: the official mkfs.jffs2 tool in mtd-utils doesn't support 4KiB
erase size and not usable for SKS8300-8X
2. Create a directory for working
3. Download official firmware for SKS8300-8X from XikeStor's official
website
4. Rename the downloaded firmware to "nos.img" and place it to the
working directory
5. Create a JFFS2 filesystem binary with the working directory
/path/to/mkfs.jffs2 -p -b -U -v -e 4KiB -x lzma \
-o nos.img.jffs2 -d /path/to/working/dir/
6. Upload the created JFFS2 filesystem binary to the device
7. Erase the "firmware" partition
mtd erase firmware
8. Write the JFFS2 filesystem binary to the "firmware" partition
mtd write /path/to/nos.img.jffs2 firmware
9. After writing, reboot the device by power cycle
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Change some debugging messages of RTL930x SerDes in the PHY driver to
pr_debug() to suppress log messages on the console.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add aux-mdio and pinctrl nodes to rtl930x.dtsi to enable handling of the
external RTL8231 GPIO expander connected via MDIO.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable HIGHMEM option to use all ranges of memory on XikeStor SKS8300-8X
that has 512MiB RAM.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable the RTL8231 MFD core driver, as well as the pinctrl/gpio driver
to allow RTL839x devices to use it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable the driver for the Realtek Otto auxiliary MDIO driver so RTL839x
devices can use it. The related node is added to the base devicetree for
rtl839x-based devices, so they can enabled and use it when required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
For RTL839x, the driver was producing frequent timeouts on bus accesses.
Increasing the timeout to the one from a recent Realtek SDK resolves
these timeouts. To minimize overhead on different SoCs, each controller
can specify their own timeout.
This also add support for the register format as used on RTL93xx.
Support is added for the RTL930x "ext gpio" controller.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
regmap_read_poll_timeout() relies on usleep_range() to time the polling
loop. With the current, rather large, scheduling interval, a short
usleep_range() may take a lot longer than expected, causing performance
issues.
Switch the driver over to using regmap_read_poll_timeout_atomic(), which
uses udelay() to time the polling loop.
For comparision, the 'ethtool -m <dev>' command is about 10 times faster
with the atomic variant.
Using 'perf -r10 ethtool -m lan25':
- Driver using regmap_read_poll_timeout():
2.0117 +- 0.0118 seconds time elapsed ( +- 0.58% )
- Driver using regmap_read_poll_timeout_atomic():
0.1674 +- 0.0250 seconds time elapsed ( +- 14.95% )
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Apply the equivalent of commit f64541db02 ("realtek: HPE 1920 8G PoE+
180W move fans to hwmon") to the 24-ports variants of the HPE 1920 PoE+
switches, with model numbers JG925A and JG926A.
Copy from the original commit message:
Move to using hwmon and gpio-fan. This is by adding gpio_fan_array to
DTS and kmod-hwmon-gpiofan to DEVICE_PACKAGES.
In combination with the new rtl8231 gpio driver the default fan
behaviour will be maximum fan speed.
Bump compat value to 1.1 due to existing config in /etc/config/system
via gpio_switch. Also notify in device compat that fan is now going to
be at bootloader setting (maximum in this case) by default unless turned
down.
As the init script 03_gpio_switches does not perform any action after
removing these devices from it, the file can be dropped.
Link: https://github.com/openwrt/openwrt/pull/17598
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GPIO numbering has changed and is not stable. As a result fan
control via gpio_switch is broken, resulting in errors:
"export_store: invalid GPIO 456"
Move to using hwmon and gpio-fan. This is by adding gpio_fan_array to
DTS and kmod-hwmon-gpiofan to DEVICE_PACKAGES.
In combination with the new rtl8231 gpio driver the default fan
behaviour will be maximum fan speed.
Bump compat value to 1.1 due to existing config in /etc/config/system
via gpio_switch. Also notify in device compat that fan is now going to
be at bootloader setting (maximum in this case) by default unless turned
down.
Signed-off-by: Evan Jobling <evan@jobling.au>
Link: https://github.com/openwrt/openwrt/pull/17605
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the base DTS file for the 16 and 24 port HPE 1920 devices
(JG923A, JG924A, JG925A, JG926A), causing the new RTL8231 MFD driver to
be loaded at start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the base DTS file for the 8 port HPE 1920 devices (JG920A,
JG921A, JG922A), causing the new RTL8231 MFD driver to be loaded at
start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This patch is also needed on bmips since it fixes issues with GPIOs not being
properly configured due to gpio_request_enable not being called on bcm63xx
devices. Therefore we can now drop the bcm63268 gpio function patch.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Update the devicetree files to switch the GS1900 devices over to the new
pinctrl and GPIO driver. Enable the drivers to ensure the nodes can be
used.
This may fix issues caused by bad RMW behaviour on the GPIO data lines,
or glitches due to setting the pin direction before the pin level.
Although the driver supports retaining GPIO state after a warm boot,
some bootloaders appear to apply a default configuration on boot, which
may cause an interrupt in PoE-PSE support.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add pending patches to add RTL8231 support as a MDIO-bus attached
multi-functional device. This includes subdrivers for the pincontrol and
GPIO features, as well as the LED matrix support.
Leave the drivers disabled until required by a device.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a disabled node for the auxiliary MDIO bus, used to manage the
RTL8231 expanders. A simple-mfd parent node is added, at the same
(implied) address as the switch@1b000000 node, as the switch drivers
should anyway transistion to MFD subdivices at some point.
Additionally, two pinctrl-single node are added to allow the MDX pins to
be muxed correctly, in case the bootloader leaves these unconfigured.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a driver that exposes the auxiliary busses, used for the RTL8231
expanders, as a proper MDIO controller. The device must be instantiated
under an MFD device, so the driver should also be compatible with SoC
managed by an external CPU via SPI.
Leave the driver disabled in builds until required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Run 'make kernel_oldconfig' to get an up-to-date config.
"# CONFIG_I2C_MUX_RTL9300 is not set" is retained, as the kernel module
build will selects CONFIG_I2C_MUX=m, on which this symbol depends.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Images for certain devices are staring to become too large, as some
device only have 6MB available in their vendor partition layout for the
initial install. This is especially pressing for bootloaders only
supporting gzip compression.
Drop some packages from DEFAULT_PACKAGES that aren't strictly required
for a factory install. The user can always install more packages later
using opkg/apk, or via a sysupgrade to a custom build.
firewall4 is kept to ensure the most recent firewall package is selected
in builds including LuCI.
ethtool is kept as a frequently used diagnostics tool.
Link: https://github.com/openwrt/openwrt/pull/17450
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add 1920-24g-poe-180w to the mac address retrieval part of 02_network to
properly set the device's port MAC addresses.
This piece was missed when this device was added.
Fixes: b948c1e39b ("realtek: add support for HPE 1920-24G PoE-180W (JG925A)")
Link: https://github.com/openwrt/openwrt/pull/17460
Signed-off-by: James Sweeney <code@swny.io>
The extraneous closing parenthesis inside the case matching breaks
syntax of the network initialization script 02_network.
/bin/board_detect: /etc/board.d/02_network:
line 40: syntax error: unexpected newline (expecting ")")
Remove this character so board init is functional again.
Fixes: c8ea1aa970 ("realtek: add support for HPE 1920-24G-PoE-370w")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware information: (largely copied from 11275be)
---------------------
The HPE 1920-24G-PoE+ (180W) (JG925A) is a switch that is
part of the 1920 family which has 180W nominal PoE+ support.
Common with HPE 1920-24G:
- RTL8382 SoC
- 24 Gigabit RJ45 ports (built-in RTL8218B, 2 external RTL8218D)
- 4 SFP ports (external RTL8214FC)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
HPE 1920-24G-PoE+ (180W):
- PoE chip
- 2 fans (40mm)
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '180'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '9'
option name 'lan16'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '10'
option name 'lan15'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '11'
option name 'lan14'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '12'
option name 'lan13'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '13'
option name 'lan12'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '14'
option name 'lan11'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '15'
option name 'lan10'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '16'
option name 'lan9'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '17'
option name 'lan24'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '18'
option name 'lan23'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '19'
option name 'lan22'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '20'
option name 'lan21'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '21'
option name 'lan20'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '22'
option name 'lan19'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '23'
option name 'lan18'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '24'
option name 'lan17'
option poe_plus '1'
option priority '2'
Signed-off-by: James Sweeney <code@swny.io>
Link: https://github.com/openwrt/openwrt/pull/17444
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The debounce-interval of a gpio-keys node should be placed in the key
node itself, not in the main node. Move the properties added earlier and
fix the key node name while we're here.
Fixes: 4357f32d41 ("realtek: debounce reset key for Zyxel GS1900")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
When the reset button is next to the SFP cages, I2C operations on the
modules might cause interference on the button's GPIO line. Add a
debounce-interval of 5 times the poll-interval to ensure the line is
actually stable for some time and not just glitching.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware information:
---------------------
The HPE 1920-24G-PoE+ (370W) (JG926A) is a switch that is
part of the 1920 family wich 370W nominal PoE+ support.
Common with HPE 1920-24G:
- RTL8382 SoC
- 24 Gigabit RJ45 ports (built-in RTL8218B, 2 external RTL8218D)
- 4 SFP ports (external RTL8214FC)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
HPE 1920-24G-PoE+ (370W):
- PoE chip
- 3 fans (40mm)
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '370'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '9'
option name 'lan16'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '10'
option name 'lan15'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '11'
option name 'lan14'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '12'
option name 'lan13'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '13'
option name 'lan12'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '14'
option name 'lan11'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '15'
option name 'lan10'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '16'
option name 'lan9'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '17'
option name 'lan24'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '18'
option name 'lan23'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '19'
option name 'lan22'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '20'
option name 'lan21'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '21'
option name 'lan20'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '22'
option name 'lan19'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '23'
option name 'lan18'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '24'
option name 'lan17'
option poe_plus '1'
option priority '2'
Signed-off-by: Evan Jobling <evan.jobling@mslsc.com.au>
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Link: https://github.com/openwrt/openwrt/pull/17436
[fix space indentation in DTS]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The HPE JG924A, JG925A and JG926A share the same base.
Prepare base device for adding the PoE enabled switch support.
Signed-off-by: Evan Jobling <evan.jobling@mslsc.com.au>
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Link: https://github.com/openwrt/openwrt/pull/17436
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900 images have been updated to have a larger firmware partition,
bumping the compatibility version to 2.0. However, since this version is
generated on first boot and the default was used, these images still
advertised 1.0 after a fresh install.
Add a new uci-defaults script that will generate the correct version for
all affected Zyxel GS1900 devices.
Fixes: 35acdbe909 ("realtek: merge Zyxel GS1900 firmware partitions")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The dual-boot partition layout for the Zyxel GS1900 switches results in
6.9MB for both kernel and rootfs. Depending on the package selection,
this may already leave no space for the user overlay.
Merge the two firmware partitions, effectively dropping dual boot
support with OpenWrt. This results in a firmware partition of 13.9MB,
which should leave some room for the future.
To maintain install capabilites on new devices, an image is required
that still fits inside the original partition. The initramfs is used as
factory install image, so ensure this meets the old size constraints.
The factory image can be flashed via the same procedure as vendor images
when reverting to stock, can be installed from stock, or can be launched
via tftpboot.
Link: https://github.com/openwrt/openwrt/issues/16439
Link: https://github.com/openwrt/openwrt/pull/16442
Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
GPIO 5 on the RTL8231 is defined reset the system, but fails to actually
do so. This triggers a kernel a number of warnings and backtrace for
GPIO pins that can sleep, such as the RTL8231's. Two warnings are
emitted by libgpiod, and a third warning by gpio-restart itself after it
fails to restart the system:
[ 106.654008] ------------[ cut here ]------------
[ 106.659240] WARNING: CPU: 0 PID: 4279 at drivers/gpio/gpiolib.c:3098 gpiod_set_value+0x7c/0x108
[ Stack dump and call trace ]
[ 106.826218] ---[ end trace d1de50b401f5a153 ]---
[ 106.962992] ------------[ cut here ]------------
[ 106.968208] WARNING: CPU: 0 PID: 4279 at drivers/gpio/gpiolib.c:3098 gpiod_set_value+0x7c/0x108
[ Stack dump and call trace ]
[ 107.136718] ---[ end trace d1de50b401f5a154 ]---
[ 111.087092] ------------[ cut here ]------------
[ 111.092271] WARNING: CPU: 0 PID: 4279 at drivers/power/reset/gpio-restart.c:46 gpio_restart_notify+0xc0/0xdc
[ Stack dump and call trace ]
[ 111.256629] ---[ end trace d1de50b401f5a155 ]---
By removing gpio-restart from this device, we skip the restart-by-GPIO
attempt and rely only on the watchdog for restarts, which is already the
de facto behaviour.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Since the start of the Realtek target OpenWrt works with RTL83XX as the
target architecture. Upstream is using MACH_REALTEK_RTL instead. To
simplify further development align that.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16963
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
mutex_destroy is missing in remove.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16926
Signed-off-by: Robert Marko <robimarko@gmail.com>
Although Zyxel XGS1210 devices are not yet officially supported there
are several patches floating around to enable them. This is a very imporant
one because it fixes a SMI misconfiguration. In the known DTS the SFP+
port settings are set as follows.
phy26: ethernet-phy@26 {
compatible = "ethernet-phy-ieee802.3-c45";
phy-is-integrated;
reg = <26>;
sds = < 8 >;
};
phy27: ethernet-phy@27 {
compatible = "ethernet-phy-ieee802.3-c45";
phy-is-integrated;
reg = <27>;
sds = < 9 >;
};
So these are PHYs linked to an internal SerDes. During initialization
rtl838x_mdio_init() generates smi_bus=0 & smi_addr=27/28 for these ports.
Although this seems like a valid configuration integrated PHYs attached
to an SerDes do not have an SMI bus. Later on the mdio reset wrongly feeds
the SMI registers and as a result the PHYs on SMI bus 0 do not work.
Without patch (loaded with rtk network on & initramfs):
...
mdio_bus mdio-bus: MDIO device at address 0 is missing.
mdio_bus mdio-bus: MDIO device at address 1 is missing.
mdio_bus mdio-bus: MDIO device at address 2 is missing.
mdio_bus mdio-bus: MDIO device at address 3 is missing.
mdio_bus mdio-bus: MDIO device at address 4 is missing.
mdio_bus mdio-bus: MDIO device at address 5 is missing.
mdio_bus mdio-bus: MDIO device at address 6 is missing.
mdio_bus mdio-bus: MDIO device at address 7 is missing.
...
rtl83xx-switch ... : no phy at 0
rtl83xx-switch ... : failed to connect to PHY: -ENODEV
rtl83xx-switch ... : error -19 setting up PHY for tree 0, switch 0, port 0
rtl83xx-switch ... : no phy at 1
rtl83xx-switch ... : failed to connect to PHY: -ENODEV
rtl83xx-switch ... : error -19 setting up PHY for tree 0, switch 0, port 1
...
With patch (loaded with rtk network on & initramfs):
...
rtl83xx-switch ... : PHY [mdio-bus:00] driver [REALTEK RTL8218D] (irq=POLL)
rtl83xx-switch ... : PHY [mdio-bus:01] driver [REALTEK RTL8218D] (irq=POLL)
...
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL930x have only 4 SMI busses (0-3) and the XGS1250 SFP port ist
directly managed. Remove the wrong configuration in the dts.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently RTL8218D detection works for a range of devices. That can lead to
false positives. E.g. RTL8218B or RTL8214FC are covered by the detection mask
as well. That is wrong. Nail detection down to the real RTL8218D phy id.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
The detection of the RTL8214C is a little complicated. Make it easier.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
Three PHYs share the same identifier. Until now we simply assume
the type depending of the bus address it is attached to. Make it
better and check the chip mode register instead.
The kernel will either detect by id/mask or by match_phy_device().
Remove the unneeded settings.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
The number of phy pages differ between RTL838X and RTL839X. Make that
clear and adapt the existing defines.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
According to the specs the RTL839x provides up to 8192 phy pages.
Especially the "raw" page 8191 is used for different initialization
tasks. Increase the limit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL930x devices need the USXGMII mode. This is a final leftover
from the 6.6 conversion.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
Easier to just use devm_platform_ioremap_resource.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16701
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware specification
----------------------
* RTL8380M SoC, 1 MIPS 4KEc core @ 500MHz
* 256MB DRAM
* 32MB NOR Flash
* 8 x 10/100/1000BASE-T ports
* 2 x SFP ports
* Power LED, Fault LED
* Reset button on front panel
* UART (115200 8N1) via populated standard pin header marked JP1
TODO: The SFP ports use a shared SCL GPIO that the driver cannot handle.
The left SFP port (lan9) is defined and fully functional while the laser
on the right SFP port (lan10) is off by default.
UART pinout
-----------
[o]ooo|JP1
| ||`------ GND
| |`------- RX
| `-------- TX
`---------- Vcc (3V3)
Installation using OEM webinterface
-----------------------------------
1. Make sure you are running OEM firmware in secondary slot
2. Install squashfs-factory.imag to primary slot by upload via http
Installation using serial interface
-----------------------------------
1. Press "a" "c" "p" during message "Enter correct key to stop autoboot"
2. Load image with "upgrade runtime <TFTP IP>:squashfs-sysupgrade.bin" command
3. Switch to primary slot with "setsys bootpartition 0"
4. Store config with "savesys"
5. Boot the image with `boota` command
Dual-boot with stock firmware using writable u-boot-env
-------------------------------------------------------
From stock to OpenWrt / primary image 1 (CLI as admin):
- > boot system image1
- > reboot
From OpenWrt to stock / boot image 2: (shell as root)
- # fw_setsys bootpartition 1
- # reboot
Debrick using serial interface
------------------------------
1. Press "a" "c" "p" during message "Enter correct key to stop autoboot"
2. Load vendor image with "upgrade runtime <TFTP IP>:LGS310xxxxx.imag"
3. switch to primary partition "setsys bootpartition 0"
4. safe config "savesys"
Further documentation
---------------------
See https://openwrt.org/toh/linksys/lgs352c
It has been developed and tested on device with v1 revision.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16068
[Add missing 'w' in name of firmware partition]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
General hardware info:
----------------------
D-Link DGS-1210-28P rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC
@500MHz, DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE
capable with a total PoE power budget of 193W.
Power over Ethernet:
--------------------
The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU. In order to enable PoE, the
realtek-poe package is required. It is installed by default, but
currently it requires the manual editing of /etc/config/poe. Keep in
mind that the port number assignment does not match on this switch,
alway 8 ports are in reversed order: 8-1, 16-9 and 24-17.
LEDs and Buttons:
-----------------
On stock firmware, the mode button is supposed to switch the LED
indicators of all port LEDs between Link Activity and PoE status. The
currently selected mode is visualized using the respective LEDs. PoE Max
indicates that the maximum PoE budget has been reached. Since there is
currently no support for this behavior, these LEDs and the mode button
can be used independently.
Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.
Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
OEM installation from Web Interface:
------------------------------------
1. Make sure you are booting using OEM in image 2 slot. If not,
switch to
image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image in vendor firmware via Tools > Backup / Upgrade
Firmware > image1
3. Toggle startup image via System > Firmware Information > Boot
from
image1
4. Tools > reboot
Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:
Boot initramfs image from U-Boot:
---------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000
openwrt-rtl838x-generic-d-link_dgs-1210-28p-f-initramfs-kernel.bin`
command
5. Boot the image with `bootm` command
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15938
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Drop config and files for Linux 5.15.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/16417
Signed-off-by: Robert Marko <robimarko@gmail.com>
Hardware information:
---------------------
- SoC: RTL8393M
- Copper phy: 6×RTL8218B
- Fibre phy: RTL8214FC
- Flash: 32MiB SPI NOR, MX25L25635FMI
- RAM: 128MiB DDR3, Micron MT41K64M16TW-107
- Serial port: ±5V serial port to RJ45, ZT3232 (MAX3232 compatible)
- +370W POE on JG928A model
Note: SFP ports currently non-functional due to missing support for
RTL8214FC on the RTL8393M target.
Updated for Linux 6.6 kernel.
Installation:
-------------
- Initial installation follows same process as HPE 1920-24G (JG924A)
- Based on prior work of Jan Hoffmann <jan@3e8.eu>
- Additional work by Andreas Böhler <dev@aboehler.at>
- PoE updates and tidy-up by Stephen Howell <howels@allthatwemight.be>
Signed-off-by: Stephen Howell <howels@allthatwemight.be>
Now that there is 6.6 support for realtek, lets encourage testing it by
making it default so 5.15 can be dropped ASAP.
Link: https://github.com/openwrt/openwrt/pull/16408
Signed-off-by: Robert Marko <robimarko@gmail.com>
Merging of the realtek 6.6 series forgot to include some final fixes
for the new MDIO driver. What was changed in last second?
1. The MDIO driver used wrong constants to make use of the raw
page (for direct register access). Provide a rawpage variable in
the bus private structure, populate it during initialization and
make use of it at the proper places
2. We always used the variable portaddr for the bus index. Usually
our driver uses either addr or port for the same meaning. Remove the
duplication and reuse the normal addr variable.
3. Drop functions rtmdio_write_page() and rtmdio_read_page(). These
only call the PHY driver read/write page functions. We know that
these will only access page 0x1f. As we have only Realtek PHYs
and our driver only reacts to this special page, just hardcode it.
Benefit is that we can use these functions for PHY detection when
read/write page functions are not yet assigned.
4. Add two new helper functions phy_port_read_paged() and
phy_port_write_paged(). These allow to access arbitrary ports on
the MDIO bus when the packages are not initialized. These will be
needed for proper RTL8218B and RTL8214FC detection in forthcoming
patches.
5. The port tracking wrongly used index 0 to mark "normal" access.
This does not allow to make a "special" access to port 0. Use
index -1 to mark "normal" access.
Provide the fix for 5.15 and 6.6 to allow for easy version
comparison.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
With commit a22d359fa5 VLAN handling was fixed for kernel 6.6.
This restored network connectivity of the devices. For easy testing
backport the fix for 5.15 too.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
On the XGS1210-12 the RTL8218D is attached via XGMII. Add this to the
supported list in the DSA driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
The DGS-1210-28MP has a LM63 fan controller connected via i2c of the
RTL8231. The clock line is always low if the property
i2c-gpio,scl-open-drain is not set; with this property, the GPIO pin is
force-drive and the clock works as expected.
The LM63 is not configured by U-Boot, thus only manual fan control is
possible by settings pwm1_enable to "1" and writing the desired values to
pwm1.
The OEM firmware drives the fan from user mode and sets it up like this:
// PWM LUT/value r/w, PWM Clock = 1.4kHz
0x4a 0x28
// Tachometer spinup disabled, spin-up cycles bypassed
0x4b 0x00
// PWM Frequency = default
0x4d 0x17
// PWM Value (28)
0x4c 0x1c
// If > 0 C, use
0x50 0x00
// PWM = 28
0x51 0x1c
// If > 51 C, use
0x52 0x33
// PWM = 44
0x53 0x2e
// Set hysteresis to 100 = default
0x4f 0x03
// Turn on automatic mode and w/p the LUT values
0x4a 0x08
A thread in the OEM firmware polls the ALERT status register for fan
failures.
Unfortunately, the lm63 kernel driver does not perform any initialization
of the chip and it does not support changing some config registers (like
PWM frequency or LUT). Hence, we are stuck with the defaults and need to do
fan control in software.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/15616
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DGS-1210-28 series was lacking full SFP support due to missing GPIOs.
Fortunately, the existing GPIO definitions of DGS-1210-52 match, this adds
the required i2c-gpio nodes to the DTS and allows hotplug SFP support.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/15616
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The CPU port of realtek switches needs some proper PVID set to handle
untagged packets. Because the ethernet driver does no special VLAN
handling (see CPU tag RVID/RVID_SEL) as of now we can only steer
untagged packets by setting PVID for the CPU port. VLAN handling has
never been perfect but 3 events made things worse.
- Commit a376508216 ("rtl83xx: dsa: Do nothing when vid 0")
- Commit e691e2b302 ("rtl83xx: dsa: reset PVID to 1 instead of 0")
- Upgrade to kernel 6.6
Reasons are:
- Rejecting VID 0 disabled Linux initialization routines
- Initialization for PVID forgot to set priv->ports[port].pvid
- Kernel 6.6 does no longer clarify CPU port as untagged
To fix this prepare the VID 0 setup inside the driver. Join all ports
to VID 0 and let no one from outsinde interfere with this setup.
Especially ignore PVID settings for the CPU port for all further
VLAN commands.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Suggested-by: Bjørn Mork <bjorn@mork.no>
Since kernel commit c5714f68a76bcad3d ("net: phylink: explicitly invalidate
link_state members in mac_config") it should be clear that link data can
only be used in mac_link_up(). Refactor that for the RTL83xx targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Some devices (e.g. HP JG924A) hand over other than expected kernel boot
arguments. Looking at these one can see:
fw_init_cmdline: fw_arg0=00020000
fw_init_cmdline: fw_arg1=00060000
fw_init_cmdline: fw_arg2=fffdffff
fw_init_cmdline: fw_arg3=0000416c
Especially fw_arg2 should be the pointer to the environment and it looks
very suspicous. It is not aligned and the address is outside KSEG0 and
KSEG1. Booting the device will result in a hang. Do better at verifying
the address.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Suggested-by: Bjørn Mork <bjorn@mork.no>
The supported_interfaces bitmap cannot be empty since mainline kernel
commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
be filled"). Fix the dsa and ethernet driver accordingly.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The DSA framework has changed a bit since 6.1, lets adapt to match.
Currently there is no one-patch-fits-all solution to directly fix
all errors up to 6.6. So cover the final differences with this
second patch.
Most notable upstream changes are:
- a88dd7538461 ("net: dsa: remove legacy_pre_march2020 detection")
- 53d04b981110 ("net: dsa: remove phylink_validate() method")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[Minor checkpatch.pl cleanups]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DSA framework has changed a bit since 5.15, lets adapt to match.
Currently there is no one-patch-fits-all solution to directly fix
all errors up to 6.6. So at least take all the already known changes
that cover differences between 5.15 and 6.1
Most notable upstream changes are:
- d3eed0e57d5d ("net: dsa: keep the bridge_dev and bridge_num as part
of the same structure")
Update of port_bridge_{join,leave}: use same helper as upstream
- c26933639b54 ("net: dsa: request drivers to perform FDB isolation")
Update of port_fdb_{add,del}, port_mdb_{add,del}
- dedd6a009f41 ("net: dsa: create a dsa_lag structure")
Update of port_lag_{join,leave}
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[align updates with upstream, add references to upstream commits]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations. All errors
that wil arise from compiling with the phy driver will be covered by
follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only adapt the failing hooks and take over the
new patch locations. All errors that wil arise from compiling with
the dsa driver will be covered by follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
A lot of stuff has been converted to the phylink_pcs_ops structure.
Adapt the ethernet driver to make use of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
We no longer are required to pass the weight to netif_napi_add.
See commit b48b89f9c189 ("net: drop the weight argument from netif_napi_add").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This is not a surprise. Before upgrade to 6.6 we refactored the mdio part of
the ethernet driver and knew that changes will come. Drop all unnecessary
stuff from the old world and adapt to the new kernel.
- remove legacy functions
- directly link new functions
- adapt to new shared base address
- remove references to old MDIO bus capabilities
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations. All errors
that will arise from compiling with the ethernet driver will be covered
by follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
With the new kernel the MDIO bus gets created after the smbus
read/write functions are used. Make use of native functions.
Relocate bus initialization into a separate function to make
patch easier to read.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Take over the new patch locations and add references to the link mode into
phylink_sfp_interface_preference[] and phylink_get_capabilities().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. As the order of the 7xx patch files seems very
strange reorder all of them according to the realtek 6.6 kernel upgrade
effort.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations.
With this patch all platform specific changes for kernel 6.6 are in place.
Realtek devices are bootable from serial console. VPE is fully functional
on devices that support it. The switch functions (ethernet and DSA) are
not enabled yet.
Boot tested on RTL8380 (Linksys LGS310C) and RTL8393 (Zyxel GS1920-24).
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
VPE in mainline kernel has changed a lot. This patch wraps up the 5.15
patch files and rebases them in one single patch on top of kernel 6.6.
Former patches are
315-irqchip-irq-realtek-rtl-add-VPE-support.patch
319-irqchip-irq-realtek-rtl-fix-VPE-affinity.patch
Submitted-by: Birger Koblitz <git@birger-koblitz.de>
Submitted-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Copy the patch files to 6.6. Both target drivers/irqchip/irq-realtek-rtl.c
and are additions and fixes for IRQ VPE handling.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Copy the patch file to 6.6. No further processing required as
it applies cleanly to the new kernel
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Due to kernel changes the patch hooks totally failed
and had to be fixed manually.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US is missing. Avoid
complaints and add it with its default 125.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Copy files and config from 5.15 kernel version. Because of the big version jump
leave out the patches for now so we can treat them individually later on.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
With commit b53202a8c3 ("realtek: switch to use generic MDIO accessor functions")
the phy access logic was enhanced. A quite big kernel patch was introduced that
allowed to make use of hardware-assisted page access like we have in the realtek
target. Basically it works the following way
- The enhanced bus intercepts page write accesses
- Currently selected pages are stored in internal vars.
- Finally only all-in-one-consistent bus/register accesses are issued
- It intercepted page changes and ensured that only a complete bus call
For the details see https://github.com/openwrt/openwrt/pull/16172
Switching over to newer kernels this patch is really hard to maintain. Its heavy
modifcations exist only in the realtek target. So it does not matter if we keep
it as an kernel modification or directly include it in our driver. To make it the
future brighter we drop this patch and take over its logic. Thus the kernel will
stay totally modification-free. What do we do?
1. Up to now the bus->priv structure directly pointed to ethernet->priv. Create an
explicit private structure rtl838x_bus_priv that not only holds the ethernet->priv
pointer but also space for some bus status tracking vars as well.
2. Wherever we use a reference to ethernet->priv directly replace that by an
additional indirection over the new rtl838x_bus_priv structure.
3. Up to now the phy flag PHY_HAS_REALTEK_PAGES identified that we can use the
alternative paged access from the patch. As this will be no longer available
remove it and provide read_page/write_page functions for each possible PHY.
These functions will be pretty standard as for other Realtek PHYs.
4. The existing mdio bus read/write function rely on the classic MII_ADDR_C45
flag - one interface for two access types. This mixup will be removed on the way
to kernel 6.6. In the future there will be two pairs of access functions. One for
classic access one for c45 style access. Rewrite our functions into 3 parts:
- a classic read/write function: ready for kernel 6.6
- a new c45 read/write function: ready for kernel 6.6
- a legacy read/write wrapper: for current 5.15 for the time being
When we switch to 6.6 we only need to remove the legacy wrappers and link the
new functions. Life can be so easy.
5. The classic read/write functions will incorporate the interception logic that
was originally in the patch.
6. The package convenience functions that were embedded in the patch get lost as
well. Rewrite them inside our phy driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[Minor checkpatch.pl cleanups]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
There is no need to keep a version specific dts directory.
Rename the folder to its standard location.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The company Zyxel rebranded some years ago.
Currently the casing is according to the old branding even
for newer devices which already use the new branding.
This commit aligns the casing of Zyxel everywhere.
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15652
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
We should setup the registers for trapping LLDP packets to the CPU.
Currently, these packets are forwarded to all ports which is not desired
behaviour.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
These registers control the handling of Link Layer Discovery Protocol
(LLDP) packets. This seems to be a typo in the naming.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
According to the Realtek SDK code, the RTL8214FC, RTL8218B and RTL8218FB
all have the same chip ID 0x6276. Let's add a constant for it, as we're
using it in more than one location.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Respect the phy-is-integrated property on ethernet-phy nodes.
There are RTL8393M switches where the PHYs at address 48 and 49 are
provided by an external RTL8214FC. Hardcoding them to use the internal
SerDes makes it impossible to use the ports connected to such an
external PHY. Respect the phy-is-integrated property on ethernet-phy
nodes as a first step to support such ports.
The potential impact for this should be limited to RTL8393 based
switches, and looking at the commit messages and device tree files of
the supported switches based on this SoC, the SFP and/or combo ports are
either not working (D-Link DGS-1210-52, Netgear GS750E, TP-Link
SG2452P/T1600G-52PS), use PHYs at a different address (Panasonic
SwitchM48EG PN28480K), or already have the phy-is-integrated property
set on the PHYs at address 48 and 49.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Daniel Golle <daniel@makrotopia.org>
The function introduced in commit 7cbfe5654d is named
filter_port_list_reverse, not filter_port_list_reversed.
Fixes the following error on hpe,1920-8g-poe-65w and
hpe,1920-8g-poe-180w.
/bin/board_detect: /etc/board.d/02_network: line 84: filter_port_list_reversed: not found
Fixes: 7cbfe5654d ("realtek: move port filtering out of uci_set_poe()")
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Sander Vanheule <sander@svanheule.net>
This device is very similar to the GS1900-24E switch (added in b515ad1),
except that the first 12 of 24 ethernet ports are capable of PoE and the
physical jacks are in the right order - unlike for the GS1900-24E, where
even and uneven ports are flipped (up <-> down on panel).
Zyxel version code for this device (-24EP) is: ABTO
Signed-off-by: Mirko Vogt <mirko-openwrt@nanl.de>
The Zyxel GS1900-8 v2 or Rev.B1 is a newer variant of the GS1900-8, but
otherwise similar to the other GS1900 switches.
Differences
------------
* Front Button labeled RESTORE
* NO Power Switch on rear
* Serial Header next to the barrel power connector
* Part Number ends 0102F
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
D-Link DGS-1210-16 hangs when rebooting and has no support for the reset
button.
Fix both by enabling the same GPIOs for reboot and the reset button as
already used for D-Link DGS-1210-20 and D-Link DGS-1210-28.
Signed-off-by: Richard Kunze <kunze@tivano.de>
Recent OEM firmware versions test the version number embedded in the uimage
"name" header field. The exact restricton is unknown, but "7.0.8.4" seems
to be the lowest number accepted on a GS110TPPv1 which already has that
version or higher.
A "9.9.9.9" version is accepted as valid by the GS110TPPv1 OEM firmware,
and considered both unique enough to identify an OpenWrt image and
moderately future proof against OEM version bumps.
This change is also boot tested on a GS108Tv3 with
"BOOT Loader Version 1.0.0.2 (2018-08-31 17:05:26 UTC)"
to verify that it doesn't break boot on older hardware.
Link: https://forum.openwrt.org/t/72510/58
Signed-off-by: Bjørn Mork <bjorn@mork.no>
PoE devices in the realtek target have the possibility to add PSE info
to the board description via 02_network. Make this available for all
targets, by moving the uci_set_poe() function to the globally available
uci-default.sh script.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
uci_set_poe() now performs two duties: filtering the list of device
ports to exclude non-PoE ports, and generating the PoE related device
config.
Extract the port filtering to an external function, which is made a bit
more readable by the use of 'sort -V [-r] | uniq -u' to filter duplicate
entries out of a (reverse) version sorted list.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The ZyXEL XGS1250-12 has a chassis fan. The fan is positioned perfectly to
provide additional cooling to the Aquantia NBase-T phys. Testing has shown
that the phys can reach temperatures upwards of 72 degrees Celsius quite
easily at about 20 degrees Celsius ambient.
Support the chassis fan to give the phys a bit of extra cooling.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
Initial conversion to new LED color/function format
and drop label format where possible. The same label
is composed at runtime.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Drop redundant label with new LED color/function format declared.
This was needed previously when the new format wasn't supported by
leds.sh functions script. Now that is supported this property
can be removed in favor of the new format.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The rtl93xx SoC supports both 1000Base-X and 10GBase-CR on its SerDes
interfaces. Enable dynamic switching between mac-signaled modes to
support 1000Base-X and 10GBase-CR on the SFP port.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch adds support for 1000Base-X and 10GBase-CR directly on the
SerDes lanes of rtl93xx SoCs.
This fixes SFP/SFP+ support on devices like the XSG1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
Commit daefc646e6 ("realtek: fix ZyXEL initramfs image generation")
fixed a shell expansion issue with zyxel-vers usage. Commit 045baca10b
("realtek: deduplicate GS1900 recipes") took care of this for the
rtl838x and rtl839x subtargets, but the single device officially
supported in rtl930x - the XGS1250-12 - was overlooked. This commit
updates the XGS1250-12 build recipe as well.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Backport merged upstream patch that adds support for firmware loader
from NVMEM or attached filesystem for Aquantia PHYs.
Refresh all kernel patches affected by this change.
Also update the path for aquantia .ko that got moved to dedicated
directory upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
[rmilecki: port to 5.15]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Refresh HSGMII patch due to recent PHY backport that cause
compilation warning for case not handled in phy_interface_num_ports.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The current dts file of dgs-1210-10p doesn't support link states
for the sfp ports (they are always up).
This patch tries to give better support for this and was run tested
on dgs-1210-10p.
It was heavily inspired from Paul Fertser, RaylynnKnight
and the author of dgs-1210-10mp-f.dts
https://forum.openwrt.org/t/dlink-dgs-1210-10p-with-glc-t-co-sfp/170928
Signed-off-by: Michel Thill <jmthill@gmail.com>
The register constants were duplicated in net/dsa/rtl83xx/debugfs.c and asm
mach-rtl838x/mach-rtl83xx.h. This commit removes this duplication.
Signed-off-by: Peter Körner <git@mazdermind.de>
According to https://svanheule.net/realtek/maple/register/led_sw_ctrl and also
drivers/net/dsa/rtl83xx/debugfs.c LED_SW_CTRL on the RTL838X should be 0xa00c
not 0x0128. Please note, that is is 0x0128 on the RTL8390/cypress SOC family.
Signed-off-by: Peter Körner <git@mazdermind.de>
the given code-format did not correctly express the condition and made the code
harder to read then necessary.
Signed-off-by: Peter Körner <git@mazdermind.de>
The GS110TUP v1 is a managed switch similar to the GS110TPP v1, but with
port 10 as SFP instead of RJ-45 and a total budget of 240 watts. Ports
1-4 support 60-watt 802.3bt PoE and ports 5-8 support 30-watt 802.3at.
The flash layout of the two switches are identical, and the U-Boot
configurations are the same except for having a different magic number,
so installation can be done via the same U-Boot method.
The following command will be needed to enable the port LEDs as per
https://forum.openwrt.org/t/72510/51 :
fw_setenv bootcmd "rtk network on; boota"
Additionally, port 9 (1000base-T from a separate QSGMII PHY) does not
function without this. Port 10 was not tested as no SFP module was
available.
Signed-off-by: Jacob Potter <jacob@j4cbo.com>
[rebase on merged flash layout]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.
Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before, PVID is reset for all ports and goes out of bounds. Also, PVID
is later changed by dsa configuration by `ip link` and `bridge vlan`
commands, this does not change the CPU port PVID and CPU PVID stays 0.
It does not allow sending packets from OpenWrt to any connected devices
unless default configuration is changed
This change iterates up to and including cpu_port and sets default PVID
to 1. For lan* ports PVID can be configured with `ip link` and `bridge
vlan` commands
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Fix incorrect register value being set for VLAN_PORT_FWD
Before, the 0b1111 would be set for the register which means outgoing
packets would receive an extra tag, corresponding to the PVID of the
port.
On untagged ports, this meant outgoing packets with a single tag.
On tagged ports, this meant outgoing QinQ packets, where the inner tag
was either the PVID of the untagged ingress port, or the already
assigned original (single) tag.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Without this, luci shows 10M full duplex when there is no link. So
explicitly set half duplex and unknown speed.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Use led_setX to determine number of LEDs per port. Introduce macros to
calculate register value and shift for particular LED in a particular
set.
Problem with previous implementation is that it uses is10G status to
determine leds per port. However with usxgmii, driver sets 10g, 5g and
2.5g so even though there are only 2 leds per port it selects 4 leds per
port
This implementation relies on configured led_set node.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Before driver code
- enabled egress filter for cpu and non-cpu ports
- enabled ingress filter for non-cpu ports
This patch explicitly enables ingress and egress filtering for non-cpu
ports and disables ingress and egress filtering for cpu port.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Currently OpenWRT does not know how to properly reset the network switch. This would result in
a switch that seemed to come up properly but was unable to handle any traffic. Presumably something
earlier in the boot chain is configuring a part of the switch that gets wiped out when its reset.
For now comment out the reset GPIO entry in the device tree until the driver better supports
bringing up the switch after a reset.
Signed-off-by: Michael 'ASAP' Weinrich <michael@a5ap.net>
The upper 16 bits of the 32 bit value encode the SoC model in BCD
notation (for example 0x83806800 on a Netgear GS108Tv3 with an
RTL8380M), so it makes more sense to output the value in hex notation
than in decimal notation.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
The MAC embedded in rtl93xx switch SoCs needs different mac mode bits set
to support 10BaseT and 100BaseT link modes. Set them accordingly.
This change has been tested on a ZyXEL XGS1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch cleans up and standardizes realtek-poe support for realtek
based switches that have supported PoE ports.
The power output of switches supported by realtek-poe package can be
configured in the 02_network ucidef_set_poe() function. This was missed
when some PoE capable switches supported by realtek-poe were added.
The realtek-poe package at one point replaced a lua-rs232 based script
and some devices were not updated to use the realtek-poe package.
Consistently add realtek-poe package to DEVICE_PACKAGES for switches
with supported PoE.
Signed-off-by: Raylynn Knight <rayknight@me.com>
This is an RTL8382-based switch with 24 copper ports + 4 SFP ports
Specifications:
---------------
* SoC: Realtek RTL8382M
* Flash: 32 MiB SPI flash
* RAM: 256 MiB
* Ethernet: 24x 10/100/1000 Mbps
* Buttons: 1x "Reset" button
* UART: 1x serial header, unpopulated
* SFP: 4 SFP ports
Works:
------
- (24) RJ-45 ethernet ports
- Switch functions
- Buttons
- Sys LED on front panel (no port LEDs)
Not yet enabled:
----------------
- Port LEDs (no driver for RTL8231 in this mode)
- SFP cages (no driver for PHY)
Install via web interface:
-------------------------
Not supported at this time.
Install via serial console/tftp:
--------------------------------
The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U6)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as soon as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWRT.
Blind install via tftp:
-----------------------
This method works when it's not feasible to install a serial header.
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
3. Watch network traffic (tcpdump or wireshark works)
4. Power on the device.
5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
6. When 192.168.0.30 makes tftp requests, release pin 16
7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Hardware information:
---------------------
- RTL8380 SoC
- 8 Gigabit RJ45 PoE ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
- PoE chip
- Fanless
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '65'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
There are two hardware models of the HPE 1920-8g-poe switch. The version
currently in the repository is the model with a PoE budget of 180W. In
preparation of the addition of the 65W model, the existing model is
renamed to clarify the hardware version it targets.
As suggested by Pawel, the 'SUPPORTED_DEVICES' includes the old target
name to enable an upgrade path of builds with the old name.
Suggested-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
Fix Spanning Tree Protocol (STP) by changing COPY2CPU which currently
makes switch to ignore Bridge Protocol Data Units (BPDUs).
Tested on Zyxel GS1900-8, 24 and 48.
Signed-off-by: Rudolf Vesely <i@rudolfvesely.com>
[ improve commit description and add new line in different sections ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The USXGMII implementation of Realtek switches can not only support
10GbE but also 2.5Gb and 5Gb on top of the usual data rates.
Mark those as supported to allow them to be negotiated.
This change has been tested on a ZyXEL XGS1250-12 with the following link
partners:
- NWA50AX Pro (2.5Gb)
- RTL8152 USB NIC (2.5Gb)
- AQC111 USB NIC (2.5Gb & 5Gb)
Gbit and 10GbE has also been tested to still work fine with a variety of
devices.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This condition was introduced in commit 51c8f76612 ("realtek: Improve
MAC config handling for all SoCs") to correctly report the speed of the
internal serdes ports as 10G, but instead makes all ports read 10G
because the or-operator should have been an and-operator.
Fixes: #9953
Fixes: 51c8f76612 ("realtek: Improve MAC config handling for all SoCs")
Signed-off-by: Peter Körner <git@mazdermind.de>
[ wrap comment to 72 column and improve commit ref ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Import commits from upstream Linux replacing some downstream patches.
Move accepted patches from pending-{5.15,6.1} to backport-{5.15,6.1}.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Hardware information:
---------------------
- RTL8380 SoC
- 8 Gigabit RJ45 PoE ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
- PoE chips: Nuvoton M0516LDE + BCM59121
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc002)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '180'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
To improve code readability in drivers/net/phy/rtl83xx-phy.c, replace
constants MMD_AN and MMD_VEND2 from drivers/net/phy/rtl83xx-phy.h with
MDIO_MMD_AN and MDIO_MMD_VEND2 from <linux/mdio.h>.
Also, replace
BIT(0) with MDIO_EEE_2_5GT,
BIT(1) with MDIO_EEE_100TX,
BIT(2) with MDIO_EEE_1000T,
BIT(9) with MDIO_AN_CTRL1_RESTART,
BIT(12) with MDIO_AN_CTRL1_ENABLE,
32 with MDIO_AN_10GBT_CTRL,
60 with MDIO_AN_EEE_ADV, and
62 with MDIO_AN_EEE_ADV2
from <linux/mdio.h>.
Suggested-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Replace BIT(x) and numerical values in drivers/net/phy/rtl83xx-phy.c
with constants from <linux/mii.h> to improve code readability.
To make reviewing easier, this commit only addresses ADVERTISE_* and
MII_PHYSID* constants.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Replace numerical values, BIT(x) and (1 << x) in
drivers/net/phy/rtl83xx-phy.c with constants from <linux/mii.h> to
improve code readability.
To make reviewing easier, this commit only addresses MII_BMCR and BMCR_*
constants.
Suggested-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Backport initial LEDs hw control support. Currently this is limited to
only rx/tx and link events for the netdev trigger but the API got
accepted and the additional modes are working on and will be backported
later.
Refresh every patch and add the additional config flag for QCA8K new
LEDs support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
One is never to write to dev->addr directly. In 6.1 it will be a const and
with the newly enabled WERROR, we get a failing grade.
Lets fix this ahead of time.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
We are missing a bunch of headers, which trigger errors on 6.1, probably
due to changed header-in-header dependencies. Best add them now.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Backport commits adding support for the MT7988 built-in switch to the
mt7530 driver.
This change results in the Kconfig symbol NET_DSA_MT7530 to be extended
by NET_DSA_MT7530_MDIO (everything formally covered by NET_DSA_MT7530)
and NET_DSA_MT7530_MMIO (a new driver for the MMIO-connected built-in
switch of the MT7988 SoC).
Select NET_DSA_MT7530_MDIO for all targets previously selecting
NET_DSA_MT7530, with the exception of mediatek/filogic which also
selects NET_DSA_MT7530_MMIO.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
All targets are bumped to 5.15. Remove the old 5.10 patches, configs
and files using:
find target/linux -iname '*-5.10' -exec rm -r {} \;
Further, remove the 5.10 include.
Signed-off-by: Nick Hainke <vincent@systemli.org>
Replace fallthrough comment with fallthrough macro for rtl838x ethernet
driver.
Fix compilarion warning:
drivers/net/ethernet/rtl838x_eth.c: In function 'rtl930x_mdio_reset':
drivers/net/ethernet/rtl838x_eth.c:1959:43: error: this statement may fall through [-Werror=implicit-fallthrough=]
1959 | private_poll_mask |= BIT(i);
drivers/net/ethernet/rtl838x_eth.c:1961:17: note: here
1961 | case PHY_INTERFACE_MODE_USXGMII:
| ^~~~
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix uninizialized variable in rtl83xx qos driver
Fix compilation error:
drivers/net/dsa/rtl83xx/qos.c: In function 'rtl838x_setup_prio2queue_matrix':
drivers/net/dsa/rtl83xx/qos.c:298:19: error: 'v' is used uninitialized [-Werror=uninitialized]
298 | v |= i << (min_queues[i] * 3);
| ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/qos.c:294:13: note: 'v' was declared here
294 | u32 v;
| ^
drivers/net/dsa/rtl83xx/qos.c: In function 'rtl83xx_setup_prio2queue_cpu_matrix':
drivers/net/dsa/rtl83xx/qos.c:320:19: error: 'v' is used uninitialized [-Werror=uninitialized]
320 | v |= max_queues[i] << (i * 3);
| ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/qos.c:316:13: note: 'v' was declared here
316 | u32 v;
| ^
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Comment unused part of realtek phy driver.
Fix compilation warning:
drivers/net/phy/rtl83xx-phy.c: In function 'rtl8380_configure_int_rtl8218b':
drivers/net/phy/rtl83xx-phy.c:747:21: error: unused variable 'ipd_flag' [-Werror=unused-variable]
747 | int ipd_flag = 1;
| ^~~~~~~~
drivers/net/phy/rtl83xx-phy.c: At top level:
drivers/net/phy/rtl83xx-phy.c:3333:13: error: 'rtl931x_sds_disable' defined but not used [-Werror=unused-function]
3333 | static void rtl931x_sds_disable(u32 sds)
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment unused part of realtek dsa driver.
Fix compilation warning:
drivers/net/dsa/rtl83xx/common.c: In function 'rtl83xx_fib_event':
drivers/net/dsa/rtl83xx/common.c:1430:58: error: unused variable 'fen6_info' [-Werror=unused-variable]
1430 | struct fib6_entry_notifier_info *fen6_info = ptr;
| ^~~~~~~~~
drivers/net/dsa/rtl83xx/common.c: At top level:
drivers/net/dsa/rtl83xx/common.c:531:12: error: 'rtl83xx_octet_cntr_alloc' defined but not used [-Werror=unused-function]
531 | static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Drop unused priv in realtek dsa driver.
Fix compilation warning:
drivers/net/dsa/rtl83xx/dsa.c: In function 'rtl83xx_port_lag_change':
drivers/net/dsa/rtl83xx/dsa.c:2016:37: error: unused variable 'priv' [-Werror=unused-variable]
2016 | struct rtl838x_switch_priv *priv = ds->priv;
| ^~~~
cc1: all warnings being treated as errors
Comment rtl838x_pie_rule_dump in realtek dsa driver for rtl83xx
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl838x.c:1294:13: error: 'rtl838x_pie_rule_dump' defined but not used [-Werror=unused-function]
1294 | static void rtl838x_pie_rule_dump(struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment multiple function in realtek dsa driver for rtl930x
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl930x.c:1463:12: error: 'rtl930x_l3_intf_add' defined but not used [-Werror=unused-function]
1463 | static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
| ^~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:1414:12: error: 'rtl930x_l3_mtu_del' defined but not used [-Werror=unused-function]
1414 | static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
| ^~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:995:12: error: 'rtl930x_l3_hash6' defined but not used [-Werror=unused-function]
995 | static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
| ^~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
drivers/net/dsa/rtl83xx/rtl930x.c:1690:13: error: 'rtl930x_read_pie_fixed_fields' defined but not used [-Werror=unused-function]
1690 | static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:1432:12: error: 'rtl930x_l3_mtu_add' defined but not used [-Werror=unused-function]
1432 | static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment rtl931x_read_pie_fixed_fields in realtek dsa driver for rtl931x
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl931x.c:1116:13: error: 'rtl931x_read_pie_fixed_fields' defined but not used [-Werror=unused-function]
1116 | static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment rtl93xx_header_vlan_set in realtek ethernet driver for rtl838x
Fix compilation warning:
drivers/net/ethernet/rtl838x_eth.c: At top level:
drivers/net/ethernet/rtl838x_eth.c:164:13: error: 'rtl93xx_header_vlan_set' defined but not used [-Werror=unused-function]
164 | static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
| ^~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
