As the bootloader is reconfiguring the RTL8231 on these devices anyway,
no pin state can be maintained over warm reboots. This results in for
example the PoE disable pin always being asserted by the bootloader.
Define the GPIO line linked to the RTL8231's reset so the MDIO subsystem
will also reset the expander on boot and ensure the line in the correct
state.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Supported devices are listed in the metadata as the first part of the
DTS compatible. This normally follows the format "vendor,device".
When updating the device name of the 180W 1920-8G PoE an underscore was
used, instead of a comma, to join the vendor and device name. This will
lead to warnings for users wanting to sysupgrade a device with an older
compatible, as the device's info does not match the one the metadata.
Fixes: 987c96e889 ("realtek: rename hpe,1920-8g-poe to match hardware")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
XikeStor (Seeker) SKS8300-8X is a 8 ports Multi-Gig switch, based on
RTL9303.
Specification:
- SoC : Realtek RTL9303
- RAM : DDR3 512 MiB
- Flash : SPI-NOR 32 MiB (Winbond W25Q256JVFIQ)
- Ethernet : 8x 1/2.5/10 Gbps (SFP+)
- LEDs/Keys (GPIO): 1x/1x
- UART : "Console" port on the front panel
- type : RS-232C
- connector : RJ-45
- settings : 9600n8
- Watchdog : Diodes PT7A7514WE
- Power : 12 VDC, 2 A
Flash instruction using initramfs image:
1. Prepare TFTP server with an IP address "192.168.2.36"
2. Connect your PC to Port1 on SKS8300-8X
3. Power on SKS8300-8X and interrupt by Ctrl + B
4. Login to the vendor CLI by Ctrl + F and "diagshell_unipoe_env"
5. Login to the U-Boot CLI by "debug_unish_env" command
6. Enable Port1 with the following commands
rtk 10g 0 fiber1g (or fiber10g if 10GBase-*R)
rtk ext-devInit 0
rtk ext-pinSet 2 0
Note: the last command sets tx-disable to low
7. Download initramfs image from TFTP server
tftpboot 0x82000000 <image name>
8. Boot with the downloaded image
bootm
9. On the initramfs image, backup the stock firmware if needed
10. Upload (or download) sysupgrade image to the device
11. Erase "firmware" partition to cleanup JFFS2 of stock FW
mtd erase firmware
12. Perform sysupgrade with the sysupgrade image
13. Wait ~120 sec to complete flashing
Notes:
- A kernel binary "nos.img" needs to be stored into JFFS2 filesystem
using 4KiB erase block instead of 64KiB.
- PT7A7514WE is handled by hardware-assited system LED output
(blinking).
- Some Japanese users asked to XikeStor about maximum power limit of
SFP+ ports and got approximate criteria:
- per port : <= 2.9 W
- total (8 ports): <= 15.8 W
MAC addresses:
eth0 : 84:E5:D8:xx:xx:37 (board-info (stock:"flash_raw"), 0x218 (hex))
(ports): 84:E5:D8:xx:xx:36 (board-info (stock:"flash_raw"), 0x1f1 (hex))
Reverting to stock firmware:
1. Prepare OpenWrt SDK to use the mkfs.jffs2 tool contained in it
Note: the official mkfs.jffs2 tool in mtd-utils doesn't support 4KiB
erase size and not usable for SKS8300-8X
2. Create a directory for working
3. Download official firmware for SKS8300-8X from XikeStor's official
website
4. Rename the downloaded firmware to "nos.img" and place it to the
working directory
5. Create a JFFS2 filesystem binary with the working directory
/path/to/mkfs.jffs2 -p -b -U -v -e 4KiB -x lzma \
-o nos.img.jffs2 -d /path/to/working/dir/
6. Upload the created JFFS2 filesystem binary to the device
7. Erase the "firmware" partition
mtd erase firmware
8. Write the JFFS2 filesystem binary to the "firmware" partition
mtd write /path/to/nos.img.jffs2 firmware
9. After writing, reboot the device by power cycle
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Change some debugging messages of RTL930x SerDes in the PHY driver to
pr_debug() to suppress log messages on the console.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add aux-mdio and pinctrl nodes to rtl930x.dtsi to enable handling of the
external RTL8231 GPIO expander connected via MDIO.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable HIGHMEM option to use all ranges of memory on XikeStor SKS8300-8X
that has 512MiB RAM.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17593
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable the RTL8231 MFD core driver, as well as the pinctrl/gpio driver
to allow RTL839x devices to use it.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Enable the driver for the Realtek Otto auxiliary MDIO driver so RTL839x
devices can use it. The related node is added to the base devicetree for
rtl839x-based devices, so they can enabled and use it when required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
For RTL839x, the driver was producing frequent timeouts on bus accesses.
Increasing the timeout to the one from a recent Realtek SDK resolves
these timeouts. To minimize overhead on different SoCs, each controller
can specify their own timeout.
This also add support for the register format as used on RTL93xx.
Support is added for the RTL930x "ext gpio" controller.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
regmap_read_poll_timeout() relies on usleep_range() to time the polling
loop. With the current, rather large, scheduling interval, a short
usleep_range() may take a lot longer than expected, causing performance
issues.
Switch the driver over to using regmap_read_poll_timeout_atomic(), which
uses udelay() to time the polling loop.
For comparision, the 'ethtool -m <dev>' command is about 10 times faster
with the atomic variant.
Using 'perf -r10 ethtool -m lan25':
- Driver using regmap_read_poll_timeout():
2.0117 +- 0.0118 seconds time elapsed ( +- 0.58% )
- Driver using regmap_read_poll_timeout_atomic():
0.1674 +- 0.0250 seconds time elapsed ( +- 14.95% )
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Apply the equivalent of commit f64541db02 ("realtek: HPE 1920 8G PoE+
180W move fans to hwmon") to the 24-ports variants of the HPE 1920 PoE+
switches, with model numbers JG925A and JG926A.
Copy from the original commit message:
Move to using hwmon and gpio-fan. This is by adding gpio_fan_array to
DTS and kmod-hwmon-gpiofan to DEVICE_PACKAGES.
In combination with the new rtl8231 gpio driver the default fan
behaviour will be maximum fan speed.
Bump compat value to 1.1 due to existing config in /etc/config/system
via gpio_switch. Also notify in device compat that fan is now going to
be at bootloader setting (maximum in this case) by default unless turned
down.
As the init script 03_gpio_switches does not perform any action after
removing these devices from it, the file can be dropped.
Link: https://github.com/openwrt/openwrt/pull/17598
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GPIO numbering has changed and is not stable. As a result fan
control via gpio_switch is broken, resulting in errors:
"export_store: invalid GPIO 456"
Move to using hwmon and gpio-fan. This is by adding gpio_fan_array to
DTS and kmod-hwmon-gpiofan to DEVICE_PACKAGES.
In combination with the new rtl8231 gpio driver the default fan
behaviour will be maximum fan speed.
Bump compat value to 1.1 due to existing config in /etc/config/system
via gpio_switch. Also notify in device compat that fan is now going to
be at bootloader setting (maximum in this case) by default unless turned
down.
Signed-off-by: Evan Jobling <evan@jobling.au>
Link: https://github.com/openwrt/openwrt/pull/17605
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the base DTS file for the 16 and 24 port HPE 1920 devices
(JG923A, JG924A, JG925A, JG926A), causing the new RTL8231 MFD driver to
be loaded at start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Update the base DTS file for the 8 port HPE 1920 devices (JG920A,
JG921A, JG922A), causing the new RTL8231 MFD driver to be loaded at
start-up.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This patch is also needed on bmips since it fixes issues with GPIOs not being
properly configured due to gpio_request_enable not being called on bcm63xx
devices. Therefore we can now drop the bcm63268 gpio function patch.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Update the devicetree files to switch the GS1900 devices over to the new
pinctrl and GPIO driver. Enable the drivers to ensure the nodes can be
used.
This may fix issues caused by bad RMW behaviour on the GPIO data lines,
or glitches due to setting the pin direction before the pin level.
Although the driver supports retaining GPIO state after a warm boot,
some bootloaders appear to apply a default configuration on boot, which
may cause an interrupt in PoE-PSE support.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add pending patches to add RTL8231 support as a MDIO-bus attached
multi-functional device. This includes subdrivers for the pincontrol and
GPIO features, as well as the LED matrix support.
Leave the drivers disabled until required by a device.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a disabled node for the auxiliary MDIO bus, used to manage the
RTL8231 expanders. A simple-mfd parent node is added, at the same
(implied) address as the switch@1b000000 node, as the switch drivers
should anyway transistion to MFD subdivices at some point.
Additionally, two pinctrl-single node are added to allow the MDX pins to
be muxed correctly, in case the bootloader leaves these unconfigured.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a driver that exposes the auxiliary busses, used for the RTL8231
expanders, as a proper MDIO controller. The device must be instantiated
under an MFD device, so the driver should also be compatible with SoC
managed by an external CPU via SPI.
Leave the driver disabled in builds until required.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Run 'make kernel_oldconfig' to get an up-to-date config.
"# CONFIG_I2C_MUX_RTL9300 is not set" is retained, as the kernel module
build will selects CONFIG_I2C_MUX=m, on which this symbol depends.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Images for certain devices are staring to become too large, as some
device only have 6MB available in their vendor partition layout for the
initial install. This is especially pressing for bootloaders only
supporting gzip compression.
Drop some packages from DEFAULT_PACKAGES that aren't strictly required
for a factory install. The user can always install more packages later
using opkg/apk, or via a sysupgrade to a custom build.
firewall4 is kept to ensure the most recent firewall package is selected
in builds including LuCI.
ethtool is kept as a frequently used diagnostics tool.
Link: https://github.com/openwrt/openwrt/pull/17450
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add 1920-24g-poe-180w to the mac address retrieval part of 02_network to
properly set the device's port MAC addresses.
This piece was missed when this device was added.
Fixes: b948c1e39b ("realtek: add support for HPE 1920-24G PoE-180W (JG925A)")
Link: https://github.com/openwrt/openwrt/pull/17460
Signed-off-by: James Sweeney <code@swny.io>
The extraneous closing parenthesis inside the case matching breaks
syntax of the network initialization script 02_network.
/bin/board_detect: /etc/board.d/02_network:
line 40: syntax error: unexpected newline (expecting ")")
Remove this character so board init is functional again.
Fixes: c8ea1aa970 ("realtek: add support for HPE 1920-24G-PoE-370w")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware information: (largely copied from 11275be)
---------------------
The HPE 1920-24G-PoE+ (180W) (JG925A) is a switch that is
part of the 1920 family which has 180W nominal PoE+ support.
Common with HPE 1920-24G:
- RTL8382 SoC
- 24 Gigabit RJ45 ports (built-in RTL8218B, 2 external RTL8218D)
- 4 SFP ports (external RTL8214FC)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
HPE 1920-24G-PoE+ (180W):
- PoE chip
- 2 fans (40mm)
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '180'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '9'
option name 'lan16'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '10'
option name 'lan15'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '11'
option name 'lan14'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '12'
option name 'lan13'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '13'
option name 'lan12'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '14'
option name 'lan11'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '15'
option name 'lan10'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '16'
option name 'lan9'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '17'
option name 'lan24'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '18'
option name 'lan23'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '19'
option name 'lan22'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '20'
option name 'lan21'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '21'
option name 'lan20'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '22'
option name 'lan19'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '23'
option name 'lan18'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '24'
option name 'lan17'
option poe_plus '1'
option priority '2'
Signed-off-by: James Sweeney <code@swny.io>
Link: https://github.com/openwrt/openwrt/pull/17444
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The debounce-interval of a gpio-keys node should be placed in the key
node itself, not in the main node. Move the properties added earlier and
fix the key node name while we're here.
Fixes: 4357f32d41 ("realtek: debounce reset key for Zyxel GS1900")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
When the reset button is next to the SFP cages, I2C operations on the
modules might cause interference on the button's GPIO line. Add a
debounce-interval of 5 times the poll-interval to ensure the line is
actually stable for some time and not just glitching.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware information:
---------------------
The HPE 1920-24G-PoE+ (370W) (JG926A) is a switch that is
part of the 1920 family wich 370W nominal PoE+ support.
Common with HPE 1920-24G:
- RTL8382 SoC
- 24 Gigabit RJ45 ports (built-in RTL8218B, 2 external RTL8218D)
- 4 SFP ports (external RTL8214FC)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
HPE 1920-24G-PoE+ (370W):
- PoE chip
- 3 fans (40mm)
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '370'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '9'
option name 'lan16'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '10'
option name 'lan15'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '11'
option name 'lan14'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '12'
option name 'lan13'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '13'
option name 'lan12'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '14'
option name 'lan11'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '15'
option name 'lan10'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '16'
option name 'lan9'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '17'
option name 'lan24'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '18'
option name 'lan23'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '19'
option name 'lan22'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '20'
option name 'lan21'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '21'
option name 'lan20'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '22'
option name 'lan19'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '23'
option name 'lan18'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '24'
option name 'lan17'
option poe_plus '1'
option priority '2'
Signed-off-by: Evan Jobling <evan.jobling@mslsc.com.au>
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Link: https://github.com/openwrt/openwrt/pull/17436
[fix space indentation in DTS]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The HPE JG924A, JG925A and JG926A share the same base.
Prepare base device for adding the PoE enabled switch support.
Signed-off-by: Evan Jobling <evan.jobling@mslsc.com.au>
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Link: https://github.com/openwrt/openwrt/pull/17436
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900 images have been updated to have a larger firmware partition,
bumping the compatibility version to 2.0. However, since this version is
generated on first boot and the default was used, these images still
advertised 1.0 after a fresh install.
Add a new uci-defaults script that will generate the correct version for
all affected Zyxel GS1900 devices.
Fixes: 35acdbe909 ("realtek: merge Zyxel GS1900 firmware partitions")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The dual-boot partition layout for the Zyxel GS1900 switches results in
6.9MB for both kernel and rootfs. Depending on the package selection,
this may already leave no space for the user overlay.
Merge the two firmware partitions, effectively dropping dual boot
support with OpenWrt. This results in a firmware partition of 13.9MB,
which should leave some room for the future.
To maintain install capabilites on new devices, an image is required
that still fits inside the original partition. The initramfs is used as
factory install image, so ensure this meets the old size constraints.
The factory image can be flashed via the same procedure as vendor images
when reverting to stock, can be installed from stock, or can be launched
via tftpboot.
Link: https://github.com/openwrt/openwrt/issues/16439
Link: https://github.com/openwrt/openwrt/pull/16442
Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
GPIO 5 on the RTL8231 is defined reset the system, but fails to actually
do so. This triggers a kernel a number of warnings and backtrace for
GPIO pins that can sleep, such as the RTL8231's. Two warnings are
emitted by libgpiod, and a third warning by gpio-restart itself after it
fails to restart the system:
[ 106.654008] ------------[ cut here ]------------
[ 106.659240] WARNING: CPU: 0 PID: 4279 at drivers/gpio/gpiolib.c:3098 gpiod_set_value+0x7c/0x108
[ Stack dump and call trace ]
[ 106.826218] ---[ end trace d1de50b401f5a153 ]---
[ 106.962992] ------------[ cut here ]------------
[ 106.968208] WARNING: CPU: 0 PID: 4279 at drivers/gpio/gpiolib.c:3098 gpiod_set_value+0x7c/0x108
[ Stack dump and call trace ]
[ 107.136718] ---[ end trace d1de50b401f5a154 ]---
[ 111.087092] ------------[ cut here ]------------
[ 111.092271] WARNING: CPU: 0 PID: 4279 at drivers/power/reset/gpio-restart.c:46 gpio_restart_notify+0xc0/0xdc
[ Stack dump and call trace ]
[ 111.256629] ---[ end trace d1de50b401f5a155 ]---
By removing gpio-restart from this device, we skip the restart-by-GPIO
attempt and rely only on the watchdog for restarts, which is already the
de facto behaviour.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Since the start of the Realtek target OpenWrt works with RTL83XX as the
target architecture. Upstream is using MACH_REALTEK_RTL instead. To
simplify further development align that.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16963
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
mutex_destroy is missing in remove.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16926
Signed-off-by: Robert Marko <robimarko@gmail.com>
Although Zyxel XGS1210 devices are not yet officially supported there
are several patches floating around to enable them. This is a very imporant
one because it fixes a SMI misconfiguration. In the known DTS the SFP+
port settings are set as follows.
phy26: ethernet-phy@26 {
compatible = "ethernet-phy-ieee802.3-c45";
phy-is-integrated;
reg = <26>;
sds = < 8 >;
};
phy27: ethernet-phy@27 {
compatible = "ethernet-phy-ieee802.3-c45";
phy-is-integrated;
reg = <27>;
sds = < 9 >;
};
So these are PHYs linked to an internal SerDes. During initialization
rtl838x_mdio_init() generates smi_bus=0 & smi_addr=27/28 for these ports.
Although this seems like a valid configuration integrated PHYs attached
to an SerDes do not have an SMI bus. Later on the mdio reset wrongly feeds
the SMI registers and as a result the PHYs on SMI bus 0 do not work.
Without patch (loaded with rtk network on & initramfs):
...
mdio_bus mdio-bus: MDIO device at address 0 is missing.
mdio_bus mdio-bus: MDIO device at address 1 is missing.
mdio_bus mdio-bus: MDIO device at address 2 is missing.
mdio_bus mdio-bus: MDIO device at address 3 is missing.
mdio_bus mdio-bus: MDIO device at address 4 is missing.
mdio_bus mdio-bus: MDIO device at address 5 is missing.
mdio_bus mdio-bus: MDIO device at address 6 is missing.
mdio_bus mdio-bus: MDIO device at address 7 is missing.
...
rtl83xx-switch ... : no phy at 0
rtl83xx-switch ... : failed to connect to PHY: -ENODEV
rtl83xx-switch ... : error -19 setting up PHY for tree 0, switch 0, port 0
rtl83xx-switch ... : no phy at 1
rtl83xx-switch ... : failed to connect to PHY: -ENODEV
rtl83xx-switch ... : error -19 setting up PHY for tree 0, switch 0, port 1
...
With patch (loaded with rtk network on & initramfs):
...
rtl83xx-switch ... : PHY [mdio-bus:00] driver [REALTEK RTL8218D] (irq=POLL)
rtl83xx-switch ... : PHY [mdio-bus:01] driver [REALTEK RTL8218D] (irq=POLL)
...
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL930x have only 4 SMI busses (0-3) and the XGS1250 SFP port ist
directly managed. Remove the wrong configuration in the dts.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
Currently RTL8218D detection works for a range of devices. That can lead to
false positives. E.g. RTL8218B or RTL8214FC are covered by the detection mask
as well. That is wrong. Nail detection down to the real RTL8218D phy id.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
The detection of the RTL8214C is a little complicated. Make it easier.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
Three PHYs share the same identifier. Until now we simply assume
the type depending of the bus address it is attached to. Make it
better and check the chip mode register instead.
The kernel will either detect by id/mask or by match_phy_device().
Remove the unneeded settings.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
The number of phy pages differ between RTL838X and RTL839X. Make that
clear and adapt the existing defines.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
According to the specs the RTL839x provides up to 8192 phy pages.
Especially the "raw" page 8191 is used for different initialization
tasks. Increase the limit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
RTL930x devices need the USXGMII mode. This is a final leftover
from the 6.6 conversion.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16457
Signed-off-by: Robert Marko <robimarko@gmail.com>
Easier to just use devm_platform_ioremap_resource.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/16701
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware specification
----------------------
* RTL8380M SoC, 1 MIPS 4KEc core @ 500MHz
* 256MB DRAM
* 32MB NOR Flash
* 8 x 10/100/1000BASE-T ports
* 2 x SFP ports
* Power LED, Fault LED
* Reset button on front panel
* UART (115200 8N1) via populated standard pin header marked JP1
TODO: The SFP ports use a shared SCL GPIO that the driver cannot handle.
The left SFP port (lan9) is defined and fully functional while the laser
on the right SFP port (lan10) is off by default.
UART pinout
-----------
[o]ooo|JP1
| ||`------ GND
| |`------- RX
| `-------- TX
`---------- Vcc (3V3)
Installation using OEM webinterface
-----------------------------------
1. Make sure you are running OEM firmware in secondary slot
2. Install squashfs-factory.imag to primary slot by upload via http
Installation using serial interface
-----------------------------------
1. Press "a" "c" "p" during message "Enter correct key to stop autoboot"
2. Load image with "upgrade runtime <TFTP IP>:squashfs-sysupgrade.bin" command
3. Switch to primary slot with "setsys bootpartition 0"
4. Store config with "savesys"
5. Boot the image with `boota` command
Dual-boot with stock firmware using writable u-boot-env
-------------------------------------------------------
From stock to OpenWrt / primary image 1 (CLI as admin):
- > boot system image1
- > reboot
From OpenWrt to stock / boot image 2: (shell as root)
- # fw_setsys bootpartition 1
- # reboot
Debrick using serial interface
------------------------------
1. Press "a" "c" "p" during message "Enter correct key to stop autoboot"
2. Load vendor image with "upgrade runtime <TFTP IP>:LGS310xxxxx.imag"
3. switch to primary partition "setsys bootpartition 0"
4. safe config "savesys"
Further documentation
---------------------
See https://openwrt.org/toh/linksys/lgs352c
It has been developed and tested on device with v1 revision.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16068
[Add missing 'w' in name of firmware partition]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
General hardware info:
----------------------
D-Link DGS-1210-28P rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC
@500MHz, DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE
capable with a total PoE power budget of 193W.
Power over Ethernet:
--------------------
The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU. In order to enable PoE, the
realtek-poe package is required. It is installed by default, but
currently it requires the manual editing of /etc/config/poe. Keep in
mind that the port number assignment does not match on this switch,
alway 8 ports are in reversed order: 8-1, 16-9 and 24-17.
LEDs and Buttons:
-----------------
On stock firmware, the mode button is supposed to switch the LED
indicators of all port LEDs between Link Activity and PoE status. The
currently selected mode is visualized using the respective LEDs. PoE Max
indicates that the maximum PoE budget has been reached. Since there is
currently no support for this behavior, these LEDs and the mode button
can be used independently.
Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.
Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
OEM installation from Web Interface:
------------------------------------
1. Make sure you are booting using OEM in image 2 slot. If not,
switch to
image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image in vendor firmware via Tools > Backup / Upgrade
Firmware > image1
3. Toggle startup image via System > Firmware Information > Boot
from
image1
4. Tools > reboot
Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:
Boot initramfs image from U-Boot:
---------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000
openwrt-rtl838x-generic-d-link_dgs-1210-28p-f-initramfs-kernel.bin`
command
5. Boot the image with `bootm` command
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15938
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Drop config and files for Linux 5.15.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/16417
Signed-off-by: Robert Marko <robimarko@gmail.com>
Hardware information:
---------------------
- SoC: RTL8393M
- Copper phy: 6×RTL8218B
- Fibre phy: RTL8214FC
- Flash: 32MiB SPI NOR, MX25L25635FMI
- RAM: 128MiB DDR3, Micron MT41K64M16TW-107
- Serial port: ±5V serial port to RJ45, ZT3232 (MAX3232 compatible)
- +370W POE on JG928A model
Note: SFP ports currently non-functional due to missing support for
RTL8214FC on the RTL8393M target.
Updated for Linux 6.6 kernel.
Installation:
-------------
- Initial installation follows same process as HPE 1920-24G (JG924A)
- Based on prior work of Jan Hoffmann <jan@3e8.eu>
- Additional work by Andreas Böhler <dev@aboehler.at>
- PoE updates and tidy-up by Stephen Howell <howels@allthatwemight.be>
Signed-off-by: Stephen Howell <howels@allthatwemight.be>
Now that there is 6.6 support for realtek, lets encourage testing it by
making it default so 5.15 can be dropped ASAP.
Link: https://github.com/openwrt/openwrt/pull/16408
Signed-off-by: Robert Marko <robimarko@gmail.com>
Merging of the realtek 6.6 series forgot to include some final fixes
for the new MDIO driver. What was changed in last second?
1. The MDIO driver used wrong constants to make use of the raw
page (for direct register access). Provide a rawpage variable in
the bus private structure, populate it during initialization and
make use of it at the proper places
2. We always used the variable portaddr for the bus index. Usually
our driver uses either addr or port for the same meaning. Remove the
duplication and reuse the normal addr variable.
3. Drop functions rtmdio_write_page() and rtmdio_read_page(). These
only call the PHY driver read/write page functions. We know that
these will only access page 0x1f. As we have only Realtek PHYs
and our driver only reacts to this special page, just hardcode it.
Benefit is that we can use these functions for PHY detection when
read/write page functions are not yet assigned.
4. Add two new helper functions phy_port_read_paged() and
phy_port_write_paged(). These allow to access arbitrary ports on
the MDIO bus when the packages are not initialized. These will be
needed for proper RTL8218B and RTL8214FC detection in forthcoming
patches.
5. The port tracking wrongly used index 0 to mark "normal" access.
This does not allow to make a "special" access to port 0. Use
index -1 to mark "normal" access.
Provide the fix for 5.15 and 6.6 to allow for easy version
comparison.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
With commit a22d359fa5 VLAN handling was fixed for kernel 6.6.
This restored network connectivity of the devices. For easy testing
backport the fix for 5.15 too.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
On the XGS1210-12 the RTL8218D is attached via XGMII. Add this to the
supported list in the DSA driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
The DGS-1210-28MP has a LM63 fan controller connected via i2c of the
RTL8231. The clock line is always low if the property
i2c-gpio,scl-open-drain is not set; with this property, the GPIO pin is
force-drive and the clock works as expected.
The LM63 is not configured by U-Boot, thus only manual fan control is
possible by settings pwm1_enable to "1" and writing the desired values to
pwm1.
The OEM firmware drives the fan from user mode and sets it up like this:
// PWM LUT/value r/w, PWM Clock = 1.4kHz
0x4a 0x28
// Tachometer spinup disabled, spin-up cycles bypassed
0x4b 0x00
// PWM Frequency = default
0x4d 0x17
// PWM Value (28)
0x4c 0x1c
// If > 0 C, use
0x50 0x00
// PWM = 28
0x51 0x1c
// If > 51 C, use
0x52 0x33
// PWM = 44
0x53 0x2e
// Set hysteresis to 100 = default
0x4f 0x03
// Turn on automatic mode and w/p the LUT values
0x4a 0x08
A thread in the OEM firmware polls the ALERT status register for fan
failures.
Unfortunately, the lm63 kernel driver does not perform any initialization
of the chip and it does not support changing some config registers (like
PWM frequency or LUT). Hence, we are stuck with the defaults and need to do
fan control in software.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/15616
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DGS-1210-28 series was lacking full SFP support due to missing GPIOs.
Fortunately, the existing GPIO definitions of DGS-1210-52 match, this adds
the required i2c-gpio nodes to the DTS and allows hotplug SFP support.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/15616
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The CPU port of realtek switches needs some proper PVID set to handle
untagged packets. Because the ethernet driver does no special VLAN
handling (see CPU tag RVID/RVID_SEL) as of now we can only steer
untagged packets by setting PVID for the CPU port. VLAN handling has
never been perfect but 3 events made things worse.
- Commit a376508216 ("rtl83xx: dsa: Do nothing when vid 0")
- Commit e691e2b302 ("rtl83xx: dsa: reset PVID to 1 instead of 0")
- Upgrade to kernel 6.6
Reasons are:
- Rejecting VID 0 disabled Linux initialization routines
- Initialization for PVID forgot to set priv->ports[port].pvid
- Kernel 6.6 does no longer clarify CPU port as untagged
To fix this prepare the VID 0 setup inside the driver. Join all ports
to VID 0 and let no one from outsinde interfere with this setup.
Especially ignore PVID settings for the CPU port for all further
VLAN commands.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Suggested-by: Bjørn Mork <bjorn@mork.no>
Since kernel commit c5714f68a76bcad3d ("net: phylink: explicitly invalidate
link_state members in mac_config") it should be clear that link data can
only be used in mac_link_up(). Refactor that for the RTL83xx targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Some devices (e.g. HP JG924A) hand over other than expected kernel boot
arguments. Looking at these one can see:
fw_init_cmdline: fw_arg0=00020000
fw_init_cmdline: fw_arg1=00060000
fw_init_cmdline: fw_arg2=fffdffff
fw_init_cmdline: fw_arg3=0000416c
Especially fw_arg2 should be the pointer to the environment and it looks
very suspicous. It is not aligned and the address is outside KSEG0 and
KSEG1. Booting the device will result in a hang. Do better at verifying
the address.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Suggested-by: Bjørn Mork <bjorn@mork.no>
The supported_interfaces bitmap cannot be empty since mainline kernel
commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
be filled"). Fix the dsa and ethernet driver accordingly.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The DSA framework has changed a bit since 6.1, lets adapt to match.
Currently there is no one-patch-fits-all solution to directly fix
all errors up to 6.6. So cover the final differences with this
second patch.
Most notable upstream changes are:
- a88dd7538461 ("net: dsa: remove legacy_pre_march2020 detection")
- 53d04b981110 ("net: dsa: remove phylink_validate() method")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[Minor checkpatch.pl cleanups]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DSA framework has changed a bit since 5.15, lets adapt to match.
Currently there is no one-patch-fits-all solution to directly fix
all errors up to 6.6. So at least take all the already known changes
that cover differences between 5.15 and 6.1
Most notable upstream changes are:
- d3eed0e57d5d ("net: dsa: keep the bridge_dev and bridge_num as part
of the same structure")
Update of port_bridge_{join,leave}: use same helper as upstream
- c26933639b54 ("net: dsa: request drivers to perform FDB isolation")
Update of port_fdb_{add,del}, port_mdb_{add,del}
- dedd6a009f41 ("net: dsa: create a dsa_lag structure")
Update of port_lag_{join,leave}
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[align updates with upstream, add references to upstream commits]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations. All errors
that wil arise from compiling with the phy driver will be covered by
follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only adapt the failing hooks and take over the
new patch locations. All errors that wil arise from compiling with
the dsa driver will be covered by follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
A lot of stuff has been converted to the phylink_pcs_ops structure.
Adapt the ethernet driver to make use of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
We no longer are required to pass the weight to netif_napi_add.
See commit b48b89f9c189 ("net: drop the weight argument from netif_napi_add").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This is not a surprise. Before upgrade to 6.6 we refactored the mdio part of
the ethernet driver and knew that changes will come. Drop all unnecessary
stuff from the old world and adapt to the new kernel.
- remove legacy functions
- directly link new functions
- adapt to new shared base address
- remove references to old MDIO bus capabilities
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations. All errors
that will arise from compiling with the ethernet driver will be covered
by follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
With the new kernel the MDIO bus gets created after the smbus
read/write functions are used. Make use of native functions.
Relocate bus initialization into a separate function to make
patch easier to read.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Take over the new patch locations and add references to the link mode into
phylink_sfp_interface_preference[] and phylink_get_capabilities().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. As the order of the 7xx patch files seems very
strange reorder all of them according to the realtek 6.6 kernel upgrade
effort.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations.
With this patch all platform specific changes for kernel 6.6 are in place.
Realtek devices are bootable from serial console. VPE is fully functional
on devices that support it. The switch functions (ethernet and DSA) are
not enabled yet.
Boot tested on RTL8380 (Linksys LGS310C) and RTL8393 (Zyxel GS1920-24).
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
VPE in mainline kernel has changed a lot. This patch wraps up the 5.15
patch files and rebases them in one single patch on top of kernel 6.6.
Former patches are
315-irqchip-irq-realtek-rtl-add-VPE-support.patch
319-irqchip-irq-realtek-rtl-fix-VPE-affinity.patch
Submitted-by: Birger Koblitz <git@birger-koblitz.de>
Submitted-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Copy the patch files to 6.6. Both target drivers/irqchip/irq-realtek-rtl.c
and are additions and fixes for IRQ VPE handling.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Copy the patch file to 6.6. No further processing required as
it applies cleanly to the new kernel
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Due to kernel changes the patch hooks totally failed
and had to be fixed manually.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US is missing. Avoid
complaints and add it with its default 125.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Copy files and config from 5.15 kernel version. Because of the big version jump
leave out the patches for now so we can treat them individually later on.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
With commit b53202a8c3 ("realtek: switch to use generic MDIO accessor functions")
the phy access logic was enhanced. A quite big kernel patch was introduced that
allowed to make use of hardware-assisted page access like we have in the realtek
target. Basically it works the following way
- The enhanced bus intercepts page write accesses
- Currently selected pages are stored in internal vars.
- Finally only all-in-one-consistent bus/register accesses are issued
- It intercepted page changes and ensured that only a complete bus call
For the details see https://github.com/openwrt/openwrt/pull/16172
Switching over to newer kernels this patch is really hard to maintain. Its heavy
modifcations exist only in the realtek target. So it does not matter if we keep
it as an kernel modification or directly include it in our driver. To make it the
future brighter we drop this patch and take over its logic. Thus the kernel will
stay totally modification-free. What do we do?
1. Up to now the bus->priv structure directly pointed to ethernet->priv. Create an
explicit private structure rtl838x_bus_priv that not only holds the ethernet->priv
pointer but also space for some bus status tracking vars as well.
2. Wherever we use a reference to ethernet->priv directly replace that by an
additional indirection over the new rtl838x_bus_priv structure.
3. Up to now the phy flag PHY_HAS_REALTEK_PAGES identified that we can use the
alternative paged access from the patch. As this will be no longer available
remove it and provide read_page/write_page functions for each possible PHY.
These functions will be pretty standard as for other Realtek PHYs.
4. The existing mdio bus read/write function rely on the classic MII_ADDR_C45
flag - one interface for two access types. This mixup will be removed on the way
to kernel 6.6. In the future there will be two pairs of access functions. One for
classic access one for c45 style access. Rewrite our functions into 3 parts:
- a classic read/write function: ready for kernel 6.6
- a new c45 read/write function: ready for kernel 6.6
- a legacy read/write wrapper: for current 5.15 for the time being
When we switch to 6.6 we only need to remove the legacy wrappers and link the
new functions. Life can be so easy.
5. The classic read/write functions will incorporate the interception logic that
was originally in the patch.
6. The package convenience functions that were embedded in the patch get lost as
well. Rewrite them inside our phy driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[Minor checkpatch.pl cleanups]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
There is no need to keep a version specific dts directory.
Rename the folder to its standard location.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The company Zyxel rebranded some years ago.
Currently the casing is according to the old branding even
for newer devices which already use the new branding.
This commit aligns the casing of Zyxel everywhere.
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15652
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
We should setup the registers for trapping LLDP packets to the CPU.
Currently, these packets are forwarded to all ports which is not desired
behaviour.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
These registers control the handling of Link Layer Discovery Protocol
(LLDP) packets. This seems to be a typo in the naming.
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
According to the Realtek SDK code, the RTL8214FC, RTL8218B and RTL8218FB
all have the same chip ID 0x6276. Let's add a constant for it, as we're
using it in more than one location.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Respect the phy-is-integrated property on ethernet-phy nodes.
There are RTL8393M switches where the PHYs at address 48 and 49 are
provided by an external RTL8214FC. Hardcoding them to use the internal
SerDes makes it impossible to use the ports connected to such an
external PHY. Respect the phy-is-integrated property on ethernet-phy
nodes as a first step to support such ports.
The potential impact for this should be limited to RTL8393 based
switches, and looking at the commit messages and device tree files of
the supported switches based on this SoC, the SFP and/or combo ports are
either not working (D-Link DGS-1210-52, Netgear GS750E, TP-Link
SG2452P/T1600G-52PS), use PHYs at a different address (Panasonic
SwitchM48EG PN28480K), or already have the phy-is-integrated property
set on the PHYs at address 48 and 49.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Daniel Golle <daniel@makrotopia.org>
The function introduced in commit 7cbfe5654d is named
filter_port_list_reverse, not filter_port_list_reversed.
Fixes the following error on hpe,1920-8g-poe-65w and
hpe,1920-8g-poe-180w.
/bin/board_detect: /etc/board.d/02_network: line 84: filter_port_list_reversed: not found
Fixes: 7cbfe5654d ("realtek: move port filtering out of uci_set_poe()")
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Acked-by: Sander Vanheule <sander@svanheule.net>
This device is very similar to the GS1900-24E switch (added in b515ad1),
except that the first 12 of 24 ethernet ports are capable of PoE and the
physical jacks are in the right order - unlike for the GS1900-24E, where
even and uneven ports are flipped (up <-> down on panel).
Zyxel version code for this device (-24EP) is: ABTO
Signed-off-by: Mirko Vogt <mirko-openwrt@nanl.de>
The Zyxel GS1900-8 v2 or Rev.B1 is a newer variant of the GS1900-8, but
otherwise similar to the other GS1900 switches.
Differences
------------
* Front Button labeled RESTORE
* NO Power Switch on rear
* Serial Header next to the barrel power connector
* Part Number ends 0102F
Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com>
D-Link DGS-1210-16 hangs when rebooting and has no support for the reset
button.
Fix both by enabling the same GPIOs for reboot and the reset button as
already used for D-Link DGS-1210-20 and D-Link DGS-1210-28.
Signed-off-by: Richard Kunze <kunze@tivano.de>
Recent OEM firmware versions test the version number embedded in the uimage
"name" header field. The exact restricton is unknown, but "7.0.8.4" seems
to be the lowest number accepted on a GS110TPPv1 which already has that
version or higher.
A "9.9.9.9" version is accepted as valid by the GS110TPPv1 OEM firmware,
and considered both unique enough to identify an OpenWrt image and
moderately future proof against OEM version bumps.
This change is also boot tested on a GS108Tv3 with
"BOOT Loader Version 1.0.0.2 (2018-08-31 17:05:26 UTC)"
to verify that it doesn't break boot on older hardware.
Link: https://forum.openwrt.org/t/72510/58
Signed-off-by: Bjørn Mork <bjorn@mork.no>
PoE devices in the realtek target have the possibility to add PSE info
to the board description via 02_network. Make this available for all
targets, by moving the uci_set_poe() function to the globally available
uci-default.sh script.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
uci_set_poe() now performs two duties: filtering the list of device
ports to exclude non-PoE ports, and generating the PoE related device
config.
Extract the port filtering to an external function, which is made a bit
more readable by the use of 'sort -V [-r] | uniq -u' to filter duplicate
entries out of a (reverse) version sorted list.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The ZyXEL XGS1250-12 has a chassis fan. The fan is positioned perfectly to
provide additional cooling to the Aquantia NBase-T phys. Testing has shown
that the phys can reach temperatures upwards of 72 degrees Celsius quite
easily at about 20 degrees Celsius ambient.
Support the chassis fan to give the phys a bit of extra cooling.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
Initial conversion to new LED color/function format
and drop label format where possible. The same label
is composed at runtime.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Drop redundant label with new LED color/function format declared.
This was needed previously when the new format wasn't supported by
leds.sh functions script. Now that is supported this property
can be removed in favor of the new format.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The rtl93xx SoC supports both 1000Base-X and 10GBase-CR on its SerDes
interfaces. Enable dynamic switching between mac-signaled modes to
support 1000Base-X and 10GBase-CR on the SFP port.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch adds support for 1000Base-X and 10GBase-CR directly on the
SerDes lanes of rtl93xx SoCs.
This fixes SFP/SFP+ support on devices like the XSG1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
Commit daefc646e6 ("realtek: fix ZyXEL initramfs image generation")
fixed a shell expansion issue with zyxel-vers usage. Commit 045baca10b
("realtek: deduplicate GS1900 recipes") took care of this for the
rtl838x and rtl839x subtargets, but the single device officially
supported in rtl930x - the XGS1250-12 - was overlooked. This commit
updates the XGS1250-12 build recipe as well.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Backport merged upstream patch that adds support for firmware loader
from NVMEM or attached filesystem for Aquantia PHYs.
Refresh all kernel patches affected by this change.
Also update the path for aquantia .ko that got moved to dedicated
directory upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
[rmilecki: port to 5.15]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Refresh HSGMII patch due to recent PHY backport that cause
compilation warning for case not handled in phy_interface_num_ports.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The current dts file of dgs-1210-10p doesn't support link states
for the sfp ports (they are always up).
This patch tries to give better support for this and was run tested
on dgs-1210-10p.
It was heavily inspired from Paul Fertser, RaylynnKnight
and the author of dgs-1210-10mp-f.dts
https://forum.openwrt.org/t/dlink-dgs-1210-10p-with-glc-t-co-sfp/170928
Signed-off-by: Michel Thill <jmthill@gmail.com>
The register constants were duplicated in net/dsa/rtl83xx/debugfs.c and asm
mach-rtl838x/mach-rtl83xx.h. This commit removes this duplication.
Signed-off-by: Peter Körner <git@mazdermind.de>
According to https://svanheule.net/realtek/maple/register/led_sw_ctrl and also
drivers/net/dsa/rtl83xx/debugfs.c LED_SW_CTRL on the RTL838X should be 0xa00c
not 0x0128. Please note, that is is 0x0128 on the RTL8390/cypress SOC family.
Signed-off-by: Peter Körner <git@mazdermind.de>
the given code-format did not correctly express the condition and made the code
harder to read then necessary.
Signed-off-by: Peter Körner <git@mazdermind.de>
The GS110TUP v1 is a managed switch similar to the GS110TPP v1, but with
port 10 as SFP instead of RJ-45 and a total budget of 240 watts. Ports
1-4 support 60-watt 802.3bt PoE and ports 5-8 support 30-watt 802.3at.
The flash layout of the two switches are identical, and the U-Boot
configurations are the same except for having a different magic number,
so installation can be done via the same U-Boot method.
The following command will be needed to enable the port LEDs as per
https://forum.openwrt.org/t/72510/51 :
fw_setenv bootcmd "rtk network on; boota"
Additionally, port 9 (1000base-T from a separate QSGMII PHY) does not
function without this. Port 10 was not tested as no SFP module was
available.
Signed-off-by: Jacob Potter <jacob@j4cbo.com>
[rebase on merged flash layout]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.
Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before, PVID is reset for all ports and goes out of bounds. Also, PVID
is later changed by dsa configuration by `ip link` and `bridge vlan`
commands, this does not change the CPU port PVID and CPU PVID stays 0.
It does not allow sending packets from OpenWrt to any connected devices
unless default configuration is changed
This change iterates up to and including cpu_port and sets default PVID
to 1. For lan* ports PVID can be configured with `ip link` and `bridge
vlan` commands
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Fix incorrect register value being set for VLAN_PORT_FWD
Before, the 0b1111 would be set for the register which means outgoing
packets would receive an extra tag, corresponding to the PVID of the
port.
On untagged ports, this meant outgoing packets with a single tag.
On tagged ports, this meant outgoing QinQ packets, where the inner tag
was either the PVID of the untagged ingress port, or the already
assigned original (single) tag.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Without this, luci shows 10M full duplex when there is no link. So
explicitly set half duplex and unknown speed.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Use led_setX to determine number of LEDs per port. Introduce macros to
calculate register value and shift for particular LED in a particular
set.
Problem with previous implementation is that it uses is10G status to
determine leds per port. However with usxgmii, driver sets 10g, 5g and
2.5g so even though there are only 2 leds per port it selects 4 leds per
port
This implementation relies on configured led_set node.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Before driver code
- enabled egress filter for cpu and non-cpu ports
- enabled ingress filter for non-cpu ports
This patch explicitly enables ingress and egress filtering for non-cpu
ports and disables ingress and egress filtering for cpu port.
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Currently OpenWRT does not know how to properly reset the network switch. This would result in
a switch that seemed to come up properly but was unable to handle any traffic. Presumably something
earlier in the boot chain is configuring a part of the switch that gets wiped out when its reset.
For now comment out the reset GPIO entry in the device tree until the driver better supports
bringing up the switch after a reset.
Signed-off-by: Michael 'ASAP' Weinrich <michael@a5ap.net>
The upper 16 bits of the 32 bit value encode the SoC model in BCD
notation (for example 0x83806800 on a Netgear GS108Tv3 with an
RTL8380M), so it makes more sense to output the value in hex notation
than in decimal notation.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
The MAC embedded in rtl93xx switch SoCs needs different mac mode bits set
to support 10BaseT and 100BaseT link modes. Set them accordingly.
This change has been tested on a ZyXEL XGS1250-12.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This patch cleans up and standardizes realtek-poe support for realtek
based switches that have supported PoE ports.
The power output of switches supported by realtek-poe package can be
configured in the 02_network ucidef_set_poe() function. This was missed
when some PoE capable switches supported by realtek-poe were added.
The realtek-poe package at one point replaced a lua-rs232 based script
and some devices were not updated to use the realtek-poe package.
Consistently add realtek-poe package to DEVICE_PACKAGES for switches
with supported PoE.
Signed-off-by: Raylynn Knight <rayknight@me.com>
This is an RTL8382-based switch with 24 copper ports + 4 SFP ports
Specifications:
---------------
* SoC: Realtek RTL8382M
* Flash: 32 MiB SPI flash
* RAM: 256 MiB
* Ethernet: 24x 10/100/1000 Mbps
* Buttons: 1x "Reset" button
* UART: 1x serial header, unpopulated
* SFP: 4 SFP ports
Works:
------
- (24) RJ-45 ethernet ports
- Switch functions
- Buttons
- Sys LED on front panel (no port LEDs)
Not yet enabled:
----------------
- Port LEDs (no driver for RTL8231 in this mode)
- SFP cages (no driver for PHY)
Install via web interface:
-------------------------
Not supported at this time.
Install via serial console/tftp:
--------------------------------
The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U6)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as soon as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWRT.
Blind install via tftp:
-----------------------
This method works when it's not feasible to install a serial header.
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
3. Watch network traffic (tcpdump or wireshark works)
4. Power on the device.
5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
6. When 192.168.0.30 makes tftp requests, release pin 16
7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Hardware information:
---------------------
- RTL8380 SoC
- 8 Gigabit RJ45 PoE ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
- PoE chip
- Fanless
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '65'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
There are two hardware models of the HPE 1920-8g-poe switch. The version
currently in the repository is the model with a PoE budget of 180W. In
preparation of the addition of the 65W model, the existing model is
renamed to clarify the hardware version it targets.
As suggested by Pawel, the 'SUPPORTED_DEVICES' includes the old target
name to enable an upgrade path of builds with the old name.
Suggested-by: Pawel Dembicki <paweldembicki@gmail.com>
Signed-off-by: Kevin Jilissen <info@kevinjilissen.nl>
Fix Spanning Tree Protocol (STP) by changing COPY2CPU which currently
makes switch to ignore Bridge Protocol Data Units (BPDUs).
Tested on Zyxel GS1900-8, 24 and 48.
Signed-off-by: Rudolf Vesely <i@rudolfvesely.com>
[ improve commit description and add new line in different sections ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The USXGMII implementation of Realtek switches can not only support
10GbE but also 2.5Gb and 5Gb on top of the usual data rates.
Mark those as supported to allow them to be negotiated.
This change has been tested on a ZyXEL XGS1250-12 with the following link
partners:
- NWA50AX Pro (2.5Gb)
- RTL8152 USB NIC (2.5Gb)
- AQC111 USB NIC (2.5Gb & 5Gb)
Gbit and 10GbE has also been tested to still work fine with a variety of
devices.
Signed-off-by: Tobias Schramm <tobias@t-sys.eu>
This condition was introduced in commit 51c8f76612 ("realtek: Improve
MAC config handling for all SoCs") to correctly report the speed of the
internal serdes ports as 10G, but instead makes all ports read 10G
because the or-operator should have been an and-operator.
Fixes: #9953
Fixes: 51c8f76612 ("realtek: Improve MAC config handling for all SoCs")
Signed-off-by: Peter Körner <git@mazdermind.de>
[ wrap comment to 72 column and improve commit ref ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Import commits from upstream Linux replacing some downstream patches.
Move accepted patches from pending-{5.15,6.1} to backport-{5.15,6.1}.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Hardware information:
---------------------
- RTL8380 SoC
- 8 Gigabit RJ45 PoE ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
- PoE chips: Nuvoton M0516LDE + BCM59121
Known issues:
---------------------
- PoE LEDs are uncontrolled.
(Manual taken from f2f09bc002)
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Example PoE config file (/etc/config/poe):
---------------------
config global
option budget '180'
config port
option enable '1'
option id '1'
option name 'lan8'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '2'
option name 'lan7'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan6'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '4'
option name 'lan5'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '5'
option name 'lan4'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '6'
option name 'lan3'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '7'
option name 'lan2'
option poe_plus '1'
option priority '2'
config port
option enable '1'
option id '8'
option name 'lan1'
option poe_plus '1'
option priority '2'
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
To improve code readability in drivers/net/phy/rtl83xx-phy.c, replace
constants MMD_AN and MMD_VEND2 from drivers/net/phy/rtl83xx-phy.h with
MDIO_MMD_AN and MDIO_MMD_VEND2 from <linux/mdio.h>.
Also, replace
BIT(0) with MDIO_EEE_2_5GT,
BIT(1) with MDIO_EEE_100TX,
BIT(2) with MDIO_EEE_1000T,
BIT(9) with MDIO_AN_CTRL1_RESTART,
BIT(12) with MDIO_AN_CTRL1_ENABLE,
32 with MDIO_AN_10GBT_CTRL,
60 with MDIO_AN_EEE_ADV, and
62 with MDIO_AN_EEE_ADV2
from <linux/mdio.h>.
Suggested-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Replace BIT(x) and numerical values in drivers/net/phy/rtl83xx-phy.c
with constants from <linux/mii.h> to improve code readability.
To make reviewing easier, this commit only addresses ADVERTISE_* and
MII_PHYSID* constants.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Replace numerical values, BIT(x) and (1 << x) in
drivers/net/phy/rtl83xx-phy.c with constants from <linux/mii.h> to
improve code readability.
To make reviewing easier, this commit only addresses MII_BMCR and BMCR_*
constants.
Suggested-by: DENG Qingfang <dqfext@gmail.com>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Backport initial LEDs hw control support. Currently this is limited to
only rx/tx and link events for the netdev trigger but the API got
accepted and the additional modes are working on and will be backported
later.
Refresh every patch and add the additional config flag for QCA8K new
LEDs support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
One is never to write to dev->addr directly. In 6.1 it will be a const and
with the newly enabled WERROR, we get a failing grade.
Lets fix this ahead of time.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
We are missing a bunch of headers, which trigger errors on 6.1, probably
due to changed header-in-header dependencies. Best add them now.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Backport commits adding support for the MT7988 built-in switch to the
mt7530 driver.
This change results in the Kconfig symbol NET_DSA_MT7530 to be extended
by NET_DSA_MT7530_MDIO (everything formally covered by NET_DSA_MT7530)
and NET_DSA_MT7530_MMIO (a new driver for the MMIO-connected built-in
switch of the MT7988 SoC).
Select NET_DSA_MT7530_MDIO for all targets previously selecting
NET_DSA_MT7530, with the exception of mediatek/filogic which also
selects NET_DSA_MT7530_MMIO.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
All targets are bumped to 5.15. Remove the old 5.10 patches, configs
and files using:
find target/linux -iname '*-5.10' -exec rm -r {} \;
Further, remove the 5.10 include.
Signed-off-by: Nick Hainke <vincent@systemli.org>
Replace fallthrough comment with fallthrough macro for rtl838x ethernet
driver.
Fix compilarion warning:
drivers/net/ethernet/rtl838x_eth.c: In function 'rtl930x_mdio_reset':
drivers/net/ethernet/rtl838x_eth.c:1959:43: error: this statement may fall through [-Werror=implicit-fallthrough=]
1959 | private_poll_mask |= BIT(i);
drivers/net/ethernet/rtl838x_eth.c:1961:17: note: here
1961 | case PHY_INTERFACE_MODE_USXGMII:
| ^~~~
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix uninizialized variable in rtl83xx qos driver
Fix compilation error:
drivers/net/dsa/rtl83xx/qos.c: In function 'rtl838x_setup_prio2queue_matrix':
drivers/net/dsa/rtl83xx/qos.c:298:19: error: 'v' is used uninitialized [-Werror=uninitialized]
298 | v |= i << (min_queues[i] * 3);
| ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/qos.c:294:13: note: 'v' was declared here
294 | u32 v;
| ^
drivers/net/dsa/rtl83xx/qos.c: In function 'rtl83xx_setup_prio2queue_cpu_matrix':
drivers/net/dsa/rtl83xx/qos.c:320:19: error: 'v' is used uninitialized [-Werror=uninitialized]
320 | v |= max_queues[i] << (i * 3);
| ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/qos.c:316:13: note: 'v' was declared here
316 | u32 v;
| ^
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Comment unused part of realtek phy driver.
Fix compilation warning:
drivers/net/phy/rtl83xx-phy.c: In function 'rtl8380_configure_int_rtl8218b':
drivers/net/phy/rtl83xx-phy.c:747:21: error: unused variable 'ipd_flag' [-Werror=unused-variable]
747 | int ipd_flag = 1;
| ^~~~~~~~
drivers/net/phy/rtl83xx-phy.c: At top level:
drivers/net/phy/rtl83xx-phy.c:3333:13: error: 'rtl931x_sds_disable' defined but not used [-Werror=unused-function]
3333 | static void rtl931x_sds_disable(u32 sds)
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment unused part of realtek dsa driver.
Fix compilation warning:
drivers/net/dsa/rtl83xx/common.c: In function 'rtl83xx_fib_event':
drivers/net/dsa/rtl83xx/common.c:1430:58: error: unused variable 'fen6_info' [-Werror=unused-variable]
1430 | struct fib6_entry_notifier_info *fen6_info = ptr;
| ^~~~~~~~~
drivers/net/dsa/rtl83xx/common.c: At top level:
drivers/net/dsa/rtl83xx/common.c:531:12: error: 'rtl83xx_octet_cntr_alloc' defined but not used [-Werror=unused-function]
531 | static int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Drop unused priv in realtek dsa driver.
Fix compilation warning:
drivers/net/dsa/rtl83xx/dsa.c: In function 'rtl83xx_port_lag_change':
drivers/net/dsa/rtl83xx/dsa.c:2016:37: error: unused variable 'priv' [-Werror=unused-variable]
2016 | struct rtl838x_switch_priv *priv = ds->priv;
| ^~~~
cc1: all warnings being treated as errors
Comment rtl838x_pie_rule_dump in realtek dsa driver for rtl83xx
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl838x.c:1294:13: error: 'rtl838x_pie_rule_dump' defined but not used [-Werror=unused-function]
1294 | static void rtl838x_pie_rule_dump(struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment multiple function in realtek dsa driver for rtl930x
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl930x.c:1463:12: error: 'rtl930x_l3_intf_add' defined but not used [-Werror=unused-function]
1463 | static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
| ^~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:1414:12: error: 'rtl930x_l3_mtu_del' defined but not used [-Werror=unused-function]
1414 | static int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)
| ^~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:995:12: error: 'rtl930x_l3_hash6' defined but not used [-Werror=unused-function]
995 | static u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)
| ^~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
drivers/net/dsa/rtl83xx/rtl930x.c:1690:13: error: 'rtl930x_read_pie_fixed_fields' defined but not used [-Werror=unused-function]
1690 | static void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/net/dsa/rtl83xx/rtl930x.c:1432:12: error: 'rtl930x_l3_mtu_add' defined but not used [-Werror=unused-function]
1432 | static int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)
| ^~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment rtl931x_read_pie_fixed_fields in realtek dsa driver for rtl931x
Fix compilation warning:
drivers/net/dsa/rtl83xx/rtl931x.c:1116:13: error: 'rtl931x_read_pie_fixed_fields' defined but not used [-Werror=unused-function]
1116 | static void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Comment rtl93xx_header_vlan_set in realtek ethernet driver for rtl838x
Fix compilation warning:
drivers/net/ethernet/rtl838x_eth.c: At top level:
drivers/net/ethernet/rtl838x_eth.c:164:13: error: 'rtl93xx_header_vlan_set' defined but not used [-Werror=unused-function]
164 | static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
| ^~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Rework exposing i2c_mii_valid_phy_id and i2c_mii_phy_addr in global
include.
Fix compilation warning:
In file included from drivers/net/phy/sfp.c:11:
./include/linux/mdio/mdio-i2c.h:27:21: error: 'i2c_mii_phy_addr' defined but not used [-Werror=unused-function]
27 | static unsigned int i2c_mii_phy_addr(int phy_id)
| ^~~~~~~~~~~~~~~~
./include/linux/mdio/mdio-i2c.h:22:13: error: 'i2c_mii_valid_phy_id' defined but not used [-Werror=unused-function]
22 | static bool i2c_mii_valid_phy_id(int phy_id)
| ^~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
PHY_INTERFACE_MODE_HSGMII was not handled in phylink_get_linkmodes and
phylink_parse_mode.
Fix compilation warning by adding it in the enum:
drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes':
drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_HSGMII' not handled in switch [-Werror=switch]
360 | switch (interface) {
| ^~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
All callers of the rtl83xx_mc_group_* functions already do the same
check, so these aren't needed.
For rtl83xx_mc_group_alloc, this branch also incorrectly returned 0
instead of a negative value. If the branch wasn't effectively dead code
anyway, this could potentially have caused bugs, as 0 is a valid
multicast group entry index.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The current implementation only works when store and load are called for
the same port without any other calls in between. This is because the
store function only saves a single port number instead of a portmask for
each group. It also doesn't take into account that the allocation of
multicast group entries might change between store/load calls.
As a result, the multicast port mask table gets corrupted. This also
includes the reserved entry for unknown multicast, which gets corrupted
even when no other mdb entries have been added.
Remove the code for storing/loading multicast groups entirely, as the
original commit message doesn't offer a convincing reason why this would
be necessary in the first place.
Fixes: 724e4af530 ("realtek: Store and Restore MC memberships for port enable/disable")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
There shouldn't be any reason to forward all multicast to the CPU. The
original commit message also doesn't provide a reason for this seemingly
unrelated change.
The current implementation of the delete method is also broken, as it
entirely removes any entry when the portmask contains only the CPU port,
even if it was explicitly created.
Fixes: 724e4af530 ("realtek: Store and Restore MC memberships for port enable/disable")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
There doesn't appear to be a reason to do this, as only the last entry
is actually reserved for unknown multicast.
This also fixes two issues:
- As the increment happened after the bounds check, the value of the
actually reserved last entry could be overwritten.
- On deletion of entries, a corresponding decrement was missing,
causing the wrong entry to be marked as free.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Actually use the index returned by rtl83xx_find_l2_cam_entry.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The port_vlan_add method may be called while a port is already a member
of that VLAN, so it needs to be able to handle changed flags. Fix it to
properly handle when the PVID or UNTAGGED flag was previously set, but
now no longer is.
To reduce duplication, move PVID configuration to a separate function.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The registers L2_PORT_STATIC_MV_ACT seem to specify the action to take
when the source address of a packet exists as a static fdb entry on
another port. By default the configured action is to drop such packets.
For standalone ports, this behaviour is undesired, as all traffic should
be forwarded to the CPU. So change the action to forward on standalone
ports.
A situation where this issue can occur is when a non-offloaded bond
interface is part of a bridge. In that case, the CPU port will have fdb
entries for devices connected to the bond interface, which are managed
by the assisted learning feature.
For now, this is only implemented for RTL838x/RTL839x, as the available
set of registers differs for the other devices.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
All ports are disabled by default, so configure the port isolation masks
and the pm field accordingly in the setup function. When port_enable is
called for a port, the isolation masks will be set up so that traffic
can flow between the port and the CPU.
While at it, change the code to also use the traffic_set method in
rtl83xx_setup, instead of writing to the RTL838x_PORT_ISO_CTRL(i)
registers directly.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Correctly update the isolation mask of the port being configured. The
port_bitmap variable should contain all other bridge members and needs
to be actually removed from the isolation mask instead of added to it.
Also actually remove the port being configured from the pm field of the
other ports, so that any other ports that are currently disabled will be
configured correctly when they are enabled.
Fixes: df8e6be59a ("rtl838x: add new architecture")
[fixed updating pm field of other ports]
Fixes: 2b88563ee5 ("realtek: update the tree to the latest refactored version")
[reintroduced incorrect pm field update]
Fixes: 27029277f9 ("realtek: add switch driver support for the RTL93XX based switches")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The switch driver actually expects every port to have a PHY handle, and
several branches in the code determine if a port is valid by checking
for a non-zero phy field.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The legacy (BSD) PTY support could open security problems in a system,
We do not need them in OpenWrt, deactivate this option in all targets.
Debian also deactivates this option.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Fix mis-typed DEVICE-MODEL in mk file for EnGenius EWS2910P.
Signed-off-by: Raylynn Knight <rayknight@me.com>
[ fix wrong SoB format and improve commit title/description ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Refresh patches which were no longer applying cleanly after a recently
added SFP quirk.
Fixes: 658b45ce48 ("generic: add quirk for HG MXPD-483II 2500M fiber SFP")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
APRESIA ApresiaLightGS120GT-SS (APLGS120GTSS) is a 16 + 4 ports gigabit
switch, based on RTL8382M.
Specifications:
- SoC : Realtek RTL8382M
- RAM : DDR3 256 MiB (Nanya NT5CC256M8JQ-EK)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x16 + 4
- port 1-8 : RTL8218B
- port 9-16 : RTL8382M, TP (SoC, RTL8218B)
- port 17-20 : RTL8214FC, TP/SFP (Combo)
- LEDs/Keys : 3x/1x
- UART : through-hole on PCB
- J6: 3.3V, TX, RX, GND from tri-angle marking side
- 115200n8
- Power : 100-120/200-240 VAC, 50/60 Hz
Max. 16 W, Avg 14 W (100 VAC)
- Plug : IEC 60320-C13
Flash instruction using factory image:
1. Boot ApresiaLightGS120GT-SS normally
2. Login to WebUI and open firmware page ("ファームウェア")
3. If the device is booted from image1, set active image for next
booting ("起動イメージ選択") to image2("イメージ2"), press apply
("適用") button and reboot the device to make booting from image2
4. On the WebUI, set active image to image1
5. Select the OpenWrt factory image and press update button ("更新")
6. Open reboot page ("再起動") and press reboot button ("再起動実行")
Notes:
- "ApresiaLightGS120GT-SS" is a model name and "APLGS120GTSS" is a model
number
- this device has 3x GPIO-controlled LEDs on PCB, but 1x LED
("green:unused") has no hole on the case
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The cameo-related recipes can also be used for APRESIA ApresiaLightGS
series devices. So create common definition for the devices manufactured
by Cameo.
And also, the model name of ApresiaLightGS120GT-SS is too long for cameo
header (max: 20 bytes), so use additional variable "CAMEO_BOARD_MODEL"
in Build/cameo-headers instead of DEVICE_MODEL to use the custom name.
(default of CAMEO_BOARD_MODEL: DEVICE_MODEL)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch renames some Cameo specific definitions for image generation.
The same format is also used on APRESIA ApresiaLightGS series devices, not
D-Link specific.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The net_event_work struct is allocated, but only freed in a single case.
Move the allocation to the branch where it is actually needed, and free
it after the work has been done.
Fixes: 03e1d93e07 ("realtek: add driver support for routing offload")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Use generic earlycon on Linux Kernel instead of initialization in platform
setup.
And also, drop bootargs with console= parameter from I-O DATA BSH-G24MB. It
uses 115200bps as baud-rate, the same as default in rtl838x.dtsi.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
On the realtek target, the subtarget makefiles include a KERNEL_PATCHVER
setting, shadowing KERNEL_PATCHVER from target/linux/realtek/Makefile.
This makes the realtek target an exception in this regard, and makes
switching kernel version a bit bothersome. Remove the overrides so all
subtargets use the same kernel version.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Adjust the wrong phy-handle definitions for the sfp ports so that they
match the correct switch ports.
Fixes: 89eb8b50d1 ("realtek: dgs-1210-10mp: add full sfp description")
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
Make the patches apply cleanly again.
Fixes: 4db8598e42 ("realtek: Do not set KERNEL_ENTRY just to avoid NO_EXCEPT_FILL")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Use the new timer driver for the RTL930x devices.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[remove old clock provider, select MIPS_EXTERNAL_TIMER and refresh
kernel config]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before calling sched_clock_register(), the timer used to drive the
scheduling clock should already be enabled. Otherwise the kernel log
will show strange time jumps during, and the watchdog might not be
pinged in a timely fashion, resulting in reboots.
[ 0.160281] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 78.104319] clocksource: Switched to clocksource realtek_otto_timer
Fixes: 3cc8011171 ("realtek: resurrect timer driver")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Because this comment is followed by another comment, nothing luckily
breaks, so only a cosmetic change.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
RTL931x kernel builds were patched to bypass the LINKER_LOAD_ADDRESS
parameter, and hardcode it to 0x80220000. This doesn't make much sense,
since value of LINKER_LOAD_ADDRESS, load-ld, only appears to be a copy
of load-y, adjusted to the linker's taste.
Dropping the hacks for bypassing LINKER_LOAD_ADDRESS results in a kernel
that actually starts booting on an RTL9313 (Netgear MS510TXM), but
currently still hangs when the kernel switches timers.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The TP-LINK TL-ST1008F has active-high LEDs, so we need a device tree
property to express this.
Signed-off-by: Lorenz Brun <lorenz@brun.one>
[Tidy up code, restrict changes to 5.15]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
On RTL931x builds, CONFIG_RTL931X was used as a stand-in for
CONFIG_NO_EXCEPT_FILL. Now that the latter is always selected for
devices in the realtek target, this hack can be removed. Resulting
device images are binary identical.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
It seems like we are offsetting the KERNEL_ENTRY to +0x400, which is
also accomplished by the NO_EXCEPT_FILL configuration option.
Since this is the default for MIPS_GENERIC_KERNEL, lets push a little
bit closer to that one by doing the same thing.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
After commit e0d2c59ee995 ("genirq: Always limit the affinity to online
CPUs", 5.10) on Linux, the cpumask passed to irq_set_affinity of irqchip
driver is limited to online CPUs. When irq_do_set_affinity called from
otto timer driver with only one secondary CPU, that CPU is not marked as
online yet, filtered out by cpu_online_mask and fall to error path.
Then, fail to set affinity for that CPU and it leads to instability of
timer on secondary CPU(s).
At least, RTL839x system will be affected.
log:
[ 37.560020] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[ 37.638025] rcu: 1-...!: (0 ticks this GP) idle=6ac/0/0x0 softirq=0/0 fqs=1 (false positive?)
[ 37.752683] (detected by 0, t=6002 jiffies, g=-1179, q=26293)
[ 37.829510] Sending NMI from CPU 0 to CPUs 1:
[ 37.886857] NMI backtrace for cpu 1 skipped: idling at r4k_wait_irqoff+0x1c/0x24
[ 37.984801] rcu: rcu_sched kthread timer wakeup didn't happen for 5999 jiffies! g-1179 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402
[ 38.132743] rcu: Possible timer handling issue on cpu=1 timer-softirq=0
[ 38.221033] rcu: rcu_sched kthread starved for 6000 jiffies! g-1179 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=1
[ 38.356336] rcu: Unless rcu_sched kthread gets sufficient CPU time, OOM is now expected behavior.
[ 38.474440] rcu: RCU grace-period kthread stack dump:
...
Replace to irq_force_affinity from irq_set_affinity and ignore
cpu_online_mask to fix the issue.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Tested-by: Olliver Schinagl <oliver@schinagl.nl>
While Linus is fine with longer code lines, comments should still be
within the 80 char limit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This is an RTL8393-based switch with 48 RJ-45 and 2 SFP ports.
Hardware
--------
SoC: Realtek RTL8393M
RAM: 128MB DDR3 (Nanya NT5CC64M16GP-DI)
FLASH: 8MB NOR (Macronix MX25L6433F)
ETH: 48x 10/100/1000 Mbps RJ-45 Ethernet
SFP: 2x SFP
BTN:
- 1x Reset button
LEDS:
- 50x Green-Amber leds: lan/sfp status
- 1x Green led: power (Always on)
UART:
- 115200-8-N-1 (CN3, pin-out on PCB)
Everything works correctly except for the 2 SFP ports that are not
working unless you enable it every boot in U-Boot with the command:
rtk network on
Installation
------------
You can install Openwrt using one of the following methods.
Warning: flashing OpenWrt will delete your current configuration.
Warning 2: if the -factory.bix file is not available anymore, you must
follow Method 2.
Method 1:
Check the firmware version currently running on your switch. If you are
running FW V1.0.1.10 or greater, you have to download the firmware
V1.0.1.8 from Netgear website and then flash this version. When the
switch restarts, it should be on version V1.0.1.8. Now you can get the
OpenWrt -factory.bix file and then flash it using the OEM web interface.
Method 2 (requires the UART connection):
Boot the -initramfs-kernel.bin image from U-Boot with these commands:
rtk network on;
tftpboot 0x8f000000 openwrt-realtek-rtl839x-netgear_gs750e-initramfs-kernel.bin;
bootm;
And then flash the -sysupgrade.bin file from OpenWrt.
Revert to stock
---------------
Get the stock firmware from the Netgear website and flash it using the
OpenWrt web interface. Remember to not keep the current configuration
and check the "Force upgrade" checkbox
Once reverted to stock the firmware could complain in the UART console
about mtdblock3 and/or mtdblock4 not being mounted correctly but it
seems to work anyway without any problems. Sample error:
mount: Mounting /dev/mtdblock4 on /mntlog failed: Input/output error
If you want to get rid of these error messages you can boot the
-initramfs-kernel.bin image from U-Boot with these commands:
rtk network on;
tftpboot 0x8f000000 openwrt-realtek-rtl839x-netgear_gs750e-initramfs-kernel.bin;
bootm;
And then erase the corresponding partitions using the command:
For mtdblock3:
mtd erase jffs2_cfg
For mtdblock4:
mtd erase jffs2_log
Now you can reboot the switch and the errors should be gone
Note
----
To get the SFP ports fully working, all the right GPIOs must be found.
In the GPL sources I found these:
- GPIO_14: SFP_TX_DIS1;
- GPIO_19: SFP_TX_DIS0;
Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
Make the patches apply cleanly again.
Fixes: 8dfe69cdfc ("kernel: update nvmem subsystem to the latest upstream")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Added the full SFP description for both SFP ports (lan9, 10) on D-Link
DGS-1210-10MP, which enables hot-plug detection of SFP modules.
Added the patch to both kernel 5.10 and 5.15 dts files.
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
Make the patches apply cleanly again.
Fixes: 8dfe69cdfc ("kernel: update nvmem subsystem to the latest upstream")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This is no longer needed now that the kernel is built with a load
address that matches the one hard-coded in the bootloader.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
In target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c,
make rtl838x_pie_rule_write() return non-zero value case of error.
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Make sure functions calling rtl838x_smi_wait_op() return its return
value in target/linux/realtek/files-5.15/drivers/net/dsa/rtl83xx/rtl838x.c.
This brings the code style in line with the rtl839x implementation.
Suggested-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
A behavioural change was introduced with commit 758c88b969 ("realtek:
Whitespace and codestyle cleanup") causing rtl838x_read_phy() and
rtl838x_write_phy() to unconditionally return -ETIMEDOUT. As a result,
probing the device during boot fails:
Error setting up netdev, freeing it again.
rtl838x-eth: probe of 1b00a300.ethernet failed with error -5
Fix the bootloop caused by this regression with kernel 5.15 on rtl838x
devices, by properly returning 0 on success.
Tested on a Netgear GS108T v3, a Netgear GS310TP v1, a Zyxel GS1900-8HP
v1 and an HPE 1920-8G.
Fixes: 758c88b969 ("realtek: Whitespace and codestyle cleanup")
Tested-by: Stijn Segers <foss@volatilesystems.org>
Tested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
Upstream generic MIPS uses 0x80100000 and 0x80100400 for the LOADADDR
and ENTRY addresses. As we do not want to diverge from upstream and
patch upstream when not needed, adjust our addresses as well to be
future proof.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
ZyXEL GS1900 devices with SoCs from both the RTL838x and RTL839x
families share the same image structure and size of the firmware
partition. Additionally, the GS1900-48 recipe provided a parameter for
the zyxel-vers command, but this parameter is not used. Deduplicate the
recipes by moving it to target/linux/realtek/image/common.mk.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The listed partition size doesn't match the original partition size, and
actually overlaps with the following partition. The partition node name
for the "firmware" partition also has an extra 'b' compared to the
partition offset.
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The GS1900-48 firmware image is identified by the 'AAHN' ID, while the
GS1900-48HP is identified by 'AAHO' [1]. The latter was used, resulting
in the following error message when upgrading via the stock web UI:
Device only can support firmware from V1.00(AAHN.0) and later version
Fix image generation by using the correct ID.
[1] https://download.zyxel.com/GS1900-48/firmware/GS1900-48_2.70(AAHN.3)C0_2.pdf
Link: https://forum.openwrt.org/t/146533
Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Suggested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
While cleaning up the makefiles for the realtek target, the order of the
default image generating commands was accidentally changed. This caused
the image signature to end up somewhere in the middle, misaligning the
rootfs. As a result, sysupgrade couldn't verify upgrade images anymore,
and devices end up in a boot loop due to the unaligned (and not found)
rootfs.
Fixes: 94d8b4852b ("realtek: Cleanup Makefiles")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The reset register on RTL93xx not merely have bits to execute
a reset of a hardware component, but also configuration bits for
reset procedures. Keep them during executing a reset.
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[backport to 5.10 kernel]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Linus prefers to have loop initializers nice and tightly scoped. In
OpenWRT this has been possible since 41a1a652fb ("kernel: backport
gnu11 upgrade").
This patch cleans up variable scope while trying to do the above for
'simple for loops'.
This cleans up and simplifies some functions and code, and pulls in
variables to a smaller scope.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Our current Makefiles a little bit messy and can be improved somewhat,
both in whitespace and in style.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
The only exception to C++ style comments are SPDX license identifier
markers at the start of C files (even headers have C style markers).
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Fix some ugly whitepsaces and codestyle issues around the realtek sources.
While this is by no means perfect, it catches what it caught.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
A full loop accessing all FDB entries can take several milliseconds
(on RTL839x about 20 ms), so give other kernel tasks a chance to run.
This is especially important for rtl83xx_port_fdb_dump which is itself
called in a loop for all ports by the kernel.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
These two functions are identical apart from writing different values to
the read/write bit. Create a new function rtl_table_exec to reduce code
duplication.
Also replace the unbounded busy-waiting loop. The new implementation may
sleep, but as the hardware typically responds before the first poll, any
callers doing many table accesses still need to make sure not to block
other kernel tasks themselves.
So far, polling timeout errors are only handled by logging an error, but
a return value is added to allow proper handling in the future.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
This function currently prints three messages for every switch port at
KERN_INFO level. This takes a considerable amount of time during bootup
and can even trigger an external watchdog.
Replace these log messages by a single one at KERN_DEBUG level.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
As learning for the CPU port is now disabled globally, the bit in the
TX header doesn't have any effect anymore. Remove it to make the header
consistent with the global configuration.
Originally, this change was intended to be applied before commit
eb456aedfe ("realtek: use assisted learning on CPU port"), which is
why the commit message incorrectly mentions that the TX header already
disables learning.
The reason for disabling learning on the CPU port in the first place is
that it doesn't work correctly when packets are trapped to the CPU and
then forwarded by the CPU to other ports. In that case, the switch would
incorrectly learn the CPU port as source. An example that triggered this
issue are Multicast Listener Reports and IGMP membership reports.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Add correct header to patche(s) to be correctly used
by git am and have better tracking of it.
See commit f1f97db627 ("realtek: Convert incorrect v5.10 patches").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
- rtl83xx_vlan_filtering()
"struct switchdev_trans *trans" parameter was removed[1] and
"struct netlink_ext_ack *extack" was added[2].
[1]: https://www.spinics.net/lists/netdev/msg712250.html
[2]: https://www.spinics.net/lists/netdev/msg722496.html
- rtl83xx_vlan_add/del()
vlan->vid_begin and vlan->vid_end were removed and vlan->vid was
added[3].
[3]: https://www.spinics.net/lists/netdev/msg712248.html
- rtl83xx_vlan_prepare()
"port_vlan_prepare" member was removed from "dsa_switch_ops" struct
in dsa.h[4] and vlan_prepare function should be called from vlan_add
function. Also, change return type of vlan_add function to int.
[4]: https://www.spinics.net/lists/netdev/msg712252.html
- rtl83xx_port_mdb_add()
"port_mdb_prepare" member in "dsa_switch_ops" struct was removed and
preparation need to be done in the function of "port_mdb_add" member
instead. And also, int type need to be returned on "port_mdb_add"
member[5].
[5]: https://www.spinics.net/lists/netdev/msg712251.html
- rtl83xx_port_pre_bridge_flags(), rtl83xx_port_bridge_flags()
The current "port_pre_bridge_flags" member and "port_bridge_flags"
member in "dsa_switch_ops" in dsa.h has flags of
"struct switchdev_brport_flags" type instead[6], so adjust to it.
And, the changed features are passed by flags.mask[7] in
rtl83xx_port_bridge_flags(), so check it before calling function
to enable/disable fieature.
[6]: https://lore.kernel.org/lkml/20210212151600.3357121-7-olteanv@gmail.com/
[7]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e18f4c18ab5b0dd47caaf8377c2e36d66f632a8c
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[shorten final return statement of rtl83xx_port_mdb_add()]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
- 007-5.16-gpio-realtek...: upstreamed on 5.16 and backported to 5.15.3
- 708-brflood-spi.patch : upstreamed
- 709-lag-offloading.patch: upstreamed
- 713-v5.12-net-dsa-... : upstreamed and some implementations are
replaced
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The following drivers were upstreamed and available on 5.15, so drop
from OpenWrt tree.
- realtek-otto-gpio (5.13)
- realtek-rtl-spi (5.12)
- realtek-rtl-intc (5.12)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
add three missing LEDs
- PoE-Max
- Link/Act
- PoE
add two missing buttons
- mode
- reset
The last was dropped in
commit 61a3d0075b ("realtek: update GPIO bindings in the dts files in dts-5.10")
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
General hardware info:
----------------------
D-Link DGS-1210-28MP rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC @ 500MHz,
DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 370W.
Power over Ethernet:
--------------------
The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU.
In order to enable PoE, the realtek-poe package is required. It is
installed by default, but currently it requires the manual editing of
/etc/config/poe. Keep in mind that the port number assignment does not
match on this switch, alway 8 ports are in reversed order: 8-1, 16-9 and
24-17.
LEDs and Buttons:
-----------------
On stock firmware, the mode button is supposed to switch the LED indicators
of all port LEDs between Link Activity and PoE status. The currently
selected mode is visualized using the respective LEDs. PoE Max indicates
that the maximum PoE budget has been reached.
Since there is currently no support for this behavior, these LEDs and
the mode button can be used independently.
Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.
Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
OEM installation from Web Interface:
------------------------------------
1. Make sure you are booting using OEM in image 2 slot. If not, switch to
image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image in vendor firmware via Tools > Backup / Upgrade
Firmware > image1
3. Toogle startup image via System > Firmware Information > Boot from
image1
4. Tools > reboot
Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:
Boot initramfs image from U-Boot:
---------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000
openwrt-rtl838x-generic-d-link_dgs-1210-28mp-f-initramfs-kernel.bin`
command
5. Boot the image with `bootm` command
Signed-off-by: Andreas Böhler <dev@aboehler.at>
should be add/delete or abbreviated add/del
Signed-off-by: Jan-Niklas Burfeind <git@aiyionpri.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
The code in dsa.c:rtl83xx_port_enable() was trying to set
vlan_port_tag_sts_ctrl while dealing with differences between SoCs.
However, not only that register has a different address, the register
structure and even the 2-bit value semantic changes for each SoC.
The vlan_port_tag_sts_ctrl field was dropped and converted into a
vlan_port_keep_incoming_tag_set() function that abstracts the different
between SoCs. The macro referencing that register migrated to the SoC
specific c file as it will be privately used by each file.
All magic numbers were converted into macros using BITMASK and
FIELD_PREP.
The vlan_port_tag_sts_ctrl debugfs was dropped for now as it is already
broken for rtl93xx. The best place for SoC specific code might be in each
respective c file and not in if/else clauses.
The final result is:
rtl838x: set ITAG_STS=TAGGED, same as before
rtl839x: set ITAG_STS=TAGGED instead of IGR_P_ITAG_KEEP=0x1, fixing
forwarding of tagged packets
rtl930x: set EGR_ITAG_STS=TAGGED instead of IGR_P_ITAG=0x1, possibly
fixing forwarding of tagged packets
rtl931x: set EGR_ITAG_STS=TAGGED instead of OTPID_KEEP=0x1, possibly
fixing forwarding of tagged packets
Without (EGR_)ITAG_STS=TAGGED, at least for rtl839x, forwarded packets
will drop the vlan tag while packets from the CPU will still have the
correct tag.
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
The rtl930x speed status registers require 4 bits to indicate the speed
status. As such, we want to divide by 8. To make things consistent with
the rest of this code, use a bitshift however.
This bug probably won't affect many users yet, as there aren't many
rtl930x switches in the wild yet with more then 10 ports, and thus a
low-impact bugfix.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[also fix port field extraction]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
After replacing the R4K event timer and clock source with the new
Realtek Otto timer, performance for RTL839x devices was severely
impacted, as reported by Hiroshi.
Research by Markus showed that after commit 4657a5301e ("realtek:
avoid busy waiting for RTL839x PHY read/write"), the ethernet driver
could only update a phy once per timer interval, which also heavily
impacted boot time. On e.g. a Zyxel GS1900-48, this added around a
minute to the time to fully initialise the switch.
By marking the otto clocksource as continuous, the kernel enables it to
be used for high resolution timers. This allows readx_poll_timeout() to
sleep for less than one system timer interval, reducing system dead
time.
Link: https://github.com/openwrt/openwrt/issues/11117
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Cc: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: INAGAKI Hiroshi <musashino.open@gmail.com> # Panasonic Switch-M48eG PN28480K
Tested-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-8G, HPE 1920-48G
In rtl83xx_set_features we set bit 3 to enable, and bit 4 to disable
checksuming. Looking at rtl93xx_set_features we however see that for
both enable and disable the same bit is used (bit 4). This can't be
right, especially as bit 4 for rtl83xx seems to be Collision threshold
occupying 2 bits. Change this to make this more logical.
Fixes: 9e8d62e421 ("realtek: enable CRC offloading")
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
L2 learning on the CPU port is currently not consistently configured and
relies on the default configuration of the device. On RTL83xx, it is
disabled for packets transmitted with a TX header, as hardware learning
corrupts the forwarding table otherwise. As a result, unneeded flooding
of traffic for the CPU port can already happen on some devices now. It
is also likely that similar issues exist on RTL93xx, which doesn't have
a field to disable learning in the TX header.
To address this, disable hardware learning for the CPU port globally on
all devices. Instead, enable assisted learning to let DSA write FDB
entries to the switch.
For now, this does not sync local/bridge entries to the switch. However,
support for that was added in Linux 5.14, so the next switch to a newer
kernel version is going to fix this.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Initialize the data structure using memset to avoid the possibility of
writing garbage values to the hardware.
Always set a valid entry type, which should fix writing unicast entries
on RTL930x.
For unicast entries, set the is_static flag to prevent the switch from
aging them out.
Also set the rvid field for unicast entries. This is not strictly
necessary, as the switch fills it in automatically from a non-zero vid.
However, this makes the code consistent with multicast entry setup.
While at it, reorder the statements and fix some style issues (double
space, comma instead of semicolon at end of statement). Also remove the
unneeded priv parameter and debug print for the multicast entry setup
function.
Fixes: cde31976e3 ("realtek: Add support for Layer 2 Multicast")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The switches support different actions for incoming ethernet multicast
frames with Reserved Multicast Addresses (01-80-C2-00-00-{01-2F}). The
current code will set the 2-bit action field to FLOOD (0x3) for most
classes, but the highest bit is always unset for the relevant control
registers. This means the DROP (0x1) action being used for these
classes; whatever class the MSB happens to be in.
For RTL838x, this results in {20,23-2F} frames being dropped, instead of
flooding all ports. On other switch generations, {0F,1F,2F} frames are
dropped. This is inconsistent, and appears to be a mistake. Remove this
inconsistency by flooding all multicast frames with RMA addresses.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The multicast setup function rtl838x_eth_set_multicast_list() checks if
the current SoC is a RTL839x family device. However, the function is
only included in the RTL838x ops table, so this path should never be
taken, making this dead code. rtl839x_eth_set_multicast_list() is
already present in the RTL839x ops table, so it should be safe to remove
this branch.
While touching the code, also re-sort the functions to match sorting
elsewhere, with rtl838x coming before rtl839x.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Currently several messages at KERN_INFO level are printed for every FDB
del/dump operation. This can cause a significant slowdown for example
while using "bridge fdb", and may even trigger a watchdog.
Remove most of these log messages, as the new L2 table debugfs node
should be a good replacement. Change the remaining messages to
KERN_DEBUG level.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Switch to a polling implementation similar to the one for RTL838x, to
allow other kernel tasks to run while waiting.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The new timer is not yet ready for all targets. Avoid interactive
questions during build
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[rename symbol to CONFIG_REALTEK_OTTO_TIMER]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the new timer driver for the RTL839X devices and remove the
no longer needed modules.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the new timer driver for the RTL838X devices. Remove the no
longer needed modules.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Provide some helpful information about the devicetree configuration of
our new driver
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct compatible order in examples]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Now that we provide a clock driver for the Reltek SOCs the CPU frequency might
change on demand. This has direct visible effects during operation
- the CEVT 4K timer is no longer a stable clocksource
- after CPU frequencies changes time calculation works wrong
- sched_clock falls back to kernel default interval (100 Hz)
- timestamps in dmesg have only 2 digits left
[ 0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ...
[ 0.060000] pid_max: default: 32768 minimum: 301
[ 0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build
[ 0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ...
Looking around where we can start the CEVT timer for RTL930X is a good basis.
Initially it was developed as a clocksource driver for the broken timer in that
specific SOC series. Afterwards it was shifted around to the CEVT location,
got SMP enablement and lost its clocksource feature. So we at least have
something to copy from. As the timers on these devices are well understood
the implementation follows this way:
- leave the RTL930X implementation as is
- provide a new driver for RTL83XX devices only
- swap RTL930X driver at a later time
Like the clock driver this patch contains a self contained module that is SOC
independet and already provides full support for the RTL838X, RTL839X and
RTL930X devices. Some of the new (or reestablished) features are:
- simplified initialization routines
- SMP setup with CPU hotplug framework
- derived from LXB clock speed
- supplied clocksource
- dedicated register functions for better readability
- documentation about some caveats
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove unused header includes, remove old CONFIG_MIPS dependency, add
REALTEK_ prefix to driver symbol]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
In *_enable_learning() only address learning should be configured, so
remove enabling forwarding. Forwarding is configured by the respective
*_enable_flood() functions.
Clean up both functions for RTL838x and RTL839x, and fix the comment on
the number of entries.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash RTL838x, RTL839x changes]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Those messages should be printed when entry was found (idx >= 0). Move
them to the right place to not print invalid entry indices.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amden commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The initial state of sds_mode in rtl9300_force_sds_mode() is null and it
will be configured in switch-case. So print message after it.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use the generic function of MIPS in Linux Kernel instead of open coding
our own initialisation.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it
will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects
this symbol, so the family check is redudant.
Furthermore, mips_cm_probe() is already called from setup_arch() in
mips/kernel/setup.c before prom_init(), and as such is not required.
Also move mips_cpc_probe() to run just before registering SMP ops.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash SMP change commits, reword commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
This patch only really has an impact on the rtl931x subtarget, which has
no devices. Noboby is currently set up to test these patches either, but
the end result is closer to MIPS_GENERIC, so I do not expect it to cause
issues.
RTL8231 and ethernet phys are not on the same bus, so separate the lock
to each own to cut off the unnecessary dependency.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The workaround for an already-enabled R4K timer used a non-existent
macro CAUSE_DC. Fix compiling by using the actual macro CAUSEF_DC.
Fixes: b7aab19585 ("realtek: SMP handling of R4K timer interrupts")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Until now there has been no good explanation why we mess with the R4K
timer on SMP. After extensive testing and looking at the SDK code it
becomes clear what it is all about.
When we disable the CEVT_R4K module (we will do with the new timer
driver) the R4K timer hardware still fires interrupts on the secondary
CPU. To get around this we have two options:
- Disable IRQ 7
- Stop the counter completely
This patch selects option two because this is the root of evil.. To be
on the safe side we will do it only in case the CEVT_R4K module is
disabled.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The scope of the SMP startup structure is wrong. It is created on the
stack and not as a global variable. This can lead to startup failures.
Fixes: 3f41360eb7 ("realtek: use upstream recommendation for CPU start")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de
OpenWRT's developer guide prefers having actual patches so they an be
sent upstream more easily.
However, in this case, Adding proper fields also allows for `git am` to
properly function. Some of these patches are quite old, and lack much
traceable history.
This commit tries to rectify that, by digging in the history to find
where and how it was first added.
It is by no means perfect and also shows some patches that should have
been long gone.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
When the realtek clock driver was introduced, CONFIG_COMMON_CLK_REALTEK
was not correctly disabled for other subtarget. Add the missing config
flag to fix compilation error on buildbot.
Fixes: 4850bd887c ("realtek: add RTL83XX clock driver")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Don't overwrite AS_DPM and L2LEARNING flags when dest_port is >= 32.
Fixes: 1773264a0c ("realtek: correct egress frame port verification")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Currently we fix interrupts/timers for the secondary CPU by patching
vsmp_init_secondary(). Get a little bit more generic and use the
upstream recommended way instead. Additionally avoid a check around
register_cps_smp_ops() because it does that itself.
See https://lkml.org/lkml/2022/9/12/522
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The interrupt controller depends on two control registers. GIMR enables
or disables interrupts and IRRx routes these to MIPS CPU interrupts 2-7.
Wiki currently states "A value of '0' (in IRRx) disconnects this input from
the output line, independent of the line's setting in GIMR."
Contrary to normal intuition this statement DOES NOT mean, that interrupts
can be disabled by IRRx alone. The sad truth was discovered by enabling
SMP for an Zyxel XGS1010 on the 930x target. It shows that driver and
interrupts behave as follows:
- Timer 0 interrupt 7 has active routing to CPU0 and no routing to CPU1
- Timer 1 interrupt 8 has no routing to CPU0 and active routing to CPU1
- Unmasking (enabling) interrupts writes 1 bits to all GIMR registers
- Masking (disabling) interrupts writes 0 bits to both GIMR registers
During operation we can encounter a situation like
- GIMR bit for a interrupt/CPU combination is set to enabed (=1)
- IRRx routing bits for a interrupt/CPU combination are set to disabed (=0)
This setting already allows the hardware to fire interrupts to the target
CPU/VPE if the other CPU/VPE is currently busy. Especially for CPU bound
timer interrupts this is lethal. If timer interrupt 7 arrives at CPU1 and
vice versa for interrupt 8 the restart trigger gets lost. The timer dies
and a msleep() operation in the kernel will halt endlessly.
Fix this by tracking the IRRx active routing setting in a new bitfield with
0="routing active" and 1="no routing". Enable interrupts in GIMR only
for a interrupt & CPU if routing is active. Thus we have
- GIMR = 0 / IRRx = 0 -> everything disabled
- GIMR = 1 / IRRx > 0 -> active and normal routing
- GIMR = 0 / IRRx > 0 -> masked (disabled) with normal routing
- GIMR = 1 / IRRx = 0 -> no longer possible
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The Build prefix is used for image build commands, while the Device
prefix should be used for base recipes for devices. Apply the same
naming convention here.
While touching the file, also fix the mixed indentation.
Suggested-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
There seems to be no reason to have the Netgear switches as part of
the main Makefile. Move it to its subtarget-specific Makefile since
it is only applicable there.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[update commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Currently supported HPE 1920 devices all have an RTL838x SoC, but there
are larger switches with RTL839x SoCs, although currently not supported.
Move the build recipe to common.mk so the larger devices can also make
use of the recipe, while moving it out of the main Makefile.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The D-Link DGS-1210 device series currently has supported devices with
both RTL838x and RTL839x SoCs. An image build recipe has been defined in
both subtarget makefiles, but these are mostly identical, save for the
SOC variable.
Move the SOC variable from the DGS-1210 build recipes to the applicable
devices, and put the remaining duplicate code in a shared Makefile.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware specification
----------------------
* RTL8393M SoC, 1 MIPS 34Kc core @ 700MHz
* 128MB DRAM
* 32MB NOR Flash
* 48 x 10/100/1000BASE-T ports
- 6 x External PHY with 8 ports (RTL8218D)
* 4 x Gigabit RJ45/SFP Combo ports
- External PHY with 4 SFP ports (RTL8214FC)
* Power LED
* Reset button on front panel
* UART (115200 8N1) via unpopulated standard 0.1" pin header marked J14
The gpio-restart node is not required but it does reset the switch.
TODO: The 4 combo ports attached to the RTL8214FC are not detect
properly. Linux kernel reports 49 and 50 as "External RTL8393 SERDES"
and 51 and 52 as "RTL8218B (external)". Those ports only work if
u-boot initialize it (for example, loading initramfs image using one
of those ports). A patch to PHY detection is needed for full support.
The firmware recovery using U-Boot is broken for all DGS-1210 tested
devices as pressing RESET does not trigger it (only if pressed from a
running stock image)
UART pinout
-----------
[o]ooo|J14
| ||`------ GND
| |`------- RX
| `-------- TX
`---------- Vcc (3V3)
Installation using OEM upgrade
------------------------------
1. Make sure you are running OEM firmware in image2 slot (logged as admin):
- > config firmware image_id 2 boot_up
- > reboot
2. Install squashfs-factory_image1.bin to image1 using (logged as admin):
- > download firmware_fromTFTP <tftpserver> factory_image1.bin
- > config firmware image_id 1 boot_up
- > reboot
Installation using serial interface
-----------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl839x-d-link_dgs-1210-52-initramfs-kernel.bin` command
5. Boot the image with `bootm` command
Once booted the initramfs, install the squashfs-sysupgrade.bin as a
normal OpenWrt system.
Dual-boot with stock firmware using writable u-boot-env
-------------------------------------------------------
From stock to OpenWrt / boot image 1 (CLI as admin):
- > config firmware image_id 1 boot_up
- > reboot
From OpenWrt to stock / boot image 2: (shell as root)
- # fw_setenv bootcmd 'run addargs ; bootm 0xb4e80000'
- # fw_setenv image '/dev/mtdblock7'
- # reboot
Debrick using serial interface
------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should
detect the switch
3. Flash the firmware.
Back to stock firmware using dual-boot
--------------------------------------
If you have serial interface, you can change u-boot env vars
interrupting the boot process. If not but you are running OpenWrt, you
can dual-boot (as mentioned eariler) and skip to step 4:
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Boot the image 2:
- set image /dev/mtdblock7; run addargs; bootm 0xb4e80000
4. Once booted, log as admin and change the boot image to 2
- > config firmware image_id 2 boot_up
- > reboot
5. After the boot, flash image1 with the vendor image
Back to stock firmware using DNA
--------------------------------
1. From an OpenWrt:
- # fw_setenv bootstop on
- # reboot
2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should
detect the switch
3. Flash the firmware.
It has been developed and tested on device with F3 revision.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
The D-Link DGS device tree was reorganized to better reflect the common
DT parts. The common include is named SOC specific (838X) and it seemed
like a good choice to add another common include in the future for the
RTL839X devices. From the current point of view this option is not really
needed.
1. The common part only includes data that matches RTL839X devices too.
2. The Panasonic DT structure avoids including the basic DTSI inside the
common DTSI.
Taking simplicity of the Panasonic include logic and in perparation to
provide DGS-1210-52 support it makes sense to harmonize this.
- rename common include to reflect its content
- move the link to the root DTSI directly to the device specific DTS
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Due to an oversight we accidentally inverted the timeout check. This
patch corrects this.
Fixes: 9cec4a0ea4 ("realtek: Use built-in functionality for timeout loop")
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[ wrap poll_timeout line to 80 char ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
In commit 81e3017609 ("realtek: clean up rtl838x MDIO busy wait loop")
a hand-crafted loop was created, that nearly exactly replicate the
iopoll's `read_poll_timeout` functionality.
Use that instead.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Add support for the TP-Link SG2210P switch. This is an RTL8380 based
switch with eight RJ-45 ports with 802.3af PoE, and two SFP ports.
This device shares the same board with the SG2008P and SG2008. To
model this, declare all the capabilities in the sg2xxx dtsi, and
disable unpopulated on the lower end models.
Specifications:
---------------
- SoC: Realtek RTL8380M
- Flash: 32 MiB SPI flash (Vendor varies)
- RAM: 256 MiB (Vendor varies)
- Ethernet: 8x 10/100/1000 Mbps with PoE (all ports)
2x SFP ports
- Buttons: 1x "Reset" button on front panel
- Power: 53.5V DC barrel jack
- UART: 1x serial header, unpopulated
- PoE: 2x TI TPS23861 I2C PoE controller
Works:
------
- (8) RJ-45 ethernet ports
- (2) SFP ports (with caveats)
- Switch functions
- System LED
Not yet enabled:
----------------
- Power-over-Ethernet (driver works, but doesn't enable "auto" mode)
- PoE LEDs
Enabling SFP ports:
-------------------
The SFP port control lines are hardwired, except for tx-disable. These
lines are controller by the RTL8231 in shift register mode. There is
no driver support for this yet.
However, to enable the lasers on SFP1 and SFP2 respectively:
echo 0x0510ff00 > /sys/kernel/debug/rtl838x/led/led_p_en_ctrl
echo 0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.26
echo 0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.24
Install via serial console/tftp:
--------------------------------
The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.
The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWrt:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U7)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as sson as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWrt.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[OpenWrt capitalisation in commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The "firmware" partition was assembled from two contiguous partitions.
This complexity is unnecessary. Instead of using mtd-concat over
"sys" and "usrimg1", simply declare the "firmware" partition to cover
the flash space instead.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The TP-Link RTL83xx based switches have their MAC address programmed
in the "para" partition. While in theory, the format of this partition
is dynamic, in practice, the MAC address appears to be located at a
consistent address. Thus, use nvmem-cells to read this MAC address.
The main MAC is required for deriving the MAC address of the switch
ports. Instead of reading it via mtd_get_mac_binary(), alias the
ethernet0 node as the label-mac-device, and use get_mac_label().
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Although PHY nodes are labeled, the port nodes were not. Labeling of
ports is useful for 'status = "disabled"' ports, which is supported
since commit 9a7f17e11f ("realtek: ignore disabled switch ports")
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The TP-Link TL-SG2008, TL-SG2008P, and TL-SG2210P use the same board.
The main difference is that some footprints are not populated in the
lower-end models. To model this with minimal duplication, move the
devicetree to a common dtsi, leaving out just the board name.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[remove port relabelling from commit message, already merged with commit
18a2b29aa1 ("realtek: tl-sg2008p: fix labeling of lan ports")]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This is an RTL8393-based switch with 802.3af on all 48 ports.
Specifications:
---------------
* SoC: Realtek RTL8393M
* Flash: 32 MiB SPI flash
* RAM: 256 MiB
* Ethernet: 48x 10/100/1000 Mbps with PoE+
* Buttons: 1x "Reset" button, 1x "Speed" button
* UART: 1x serial header, unpopulated
* PoE: 12x TI TPS23861 I2C PoE controller, 384W PoE budget
* SFP: 4 SFP ports
Works:
------
- (48) RJ-45 ethernet ports
- Switch functions
- Buttons
- All LEDs on front panel except port LEDs
- Fan monitoring and basic control
Not yet enabled:
----------------
- PoE - ICs are not in AUTO mode, so the kernel driver is not usable
- Port LEDs
- SFP cages
Install via web interface:
-------------------------
Not supported at this time.
Install via serial console/tftp:
--------------------------------
The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U6)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as soon as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWRT.
Blind install via tftp:
-----------------------
This method works when it's not feasible to install a serial header.
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
3. Watch network traffic (tcpdump or wireshark works)
4. Power on the device.
5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
6. When 192.168.0.30 makes tftp requests, release pin 16
7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT
Signed-off-by: Andreas Böhler <dev@aboehler.at>
The previous fixup was incomplete, and the offsets for the
queue and crc_error cpu_tag bitfields were still wrong on
RTL839x.
Fixes: 545c6113c9 ("realtek: fix RTL838x receive tag decoding")
Suggested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Commit dc9cc0d3e2 ("realtek: add QoS and rate control") replaced a
16 bit reserved field in the RTL83xx packet header with the initial
cpu_tag word, shifting the real cpu_tag fields by one. Adjusting for
this new shift was partially forgotten in the new RX tag decoders.
This caused the switch to block IGMP, effectively blocking IPv4
multicast.
The bug was partially fixed by commit 9d847244d9 ("realtek: fix
RTL839X receive tag decoding")
Fix on RTL838x too, including correct NIC_RX_REASON_SPECIAL_TRAP value.
Suggested-by: Jan Hoffmann <jan@3e8.eu>
Fixes: dc9cc0d3e2 ("realtek: add QoS and rate control")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
8 and 16 bit writes to the GPIO peripheral are apparently not supported,
and only worked most of the time. This resulted in garbabe writes to the
interrupt mask registers, causing spurious unhandled interrupts, which
could lead to CPU lock-ups as these kept retriggering.
Instead of clearing these spurious interrupt when they occur, the
upstream patch will just make sure all register writes have the intended
result, so these don't happen at all.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Since introduction of clock driver we have a new kernel config
setting. Provide an initial value for the 930x targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Some devices have wrong/empty values in the PLL registers. Work
around that by reporting the default values.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The SG2008P has its ethernet ports in the rear, and LEDs in the front.
The ports should be labeled lan8->lan1, not lan1->lan8. To resolve
this, fix the phy mapping in the "ports" node.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Address 0x30 is a "broadcast" address for the TPS23861. It should not
be used by drivers, as all TPS23861 devices on the bus are supposed to
respond. Change this to the correct address, 0x28.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
When marking a switch port as disabled in the device tree, by using
'status = "disabled";', the switch driver fails on boot, causing a
restart:
CPU 0 Unable to handle kernel paging request at virtual address
00000000, epc == 802c3064, ra == 8022b4b4
[ ... ]
Call Trace:
[<802c3064>] strlen+0x0/0x2c
[<8022b4b4>] start_creating.part.0+0x78/0x194
[<8022bd3c>] debugfs_create_dir+0x44/0x1c0
[<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258
[<80397508>] rtl838x_dbgfs_init+0xe0/0x56c
This is caused by the DSA subsystem (mostly) ignoring the port, while
rtl83xx_mdio_probe() still extracts some details on this disabled port
from the device tree, resulting in the usage of a NULL pointer where a
port name is expected.
By not probing ignoring disabled ports, no attempt is made to create a
debugfs directory later. The device then boots as expected without the
disabled port.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work
we need to change some nodes:
- define the external oscillator speed (25MHz)
- define SRAM
- add clock controller
- Add second CPU for RTL839X
- map all devices to new clocks
- Remove dummy LXB clock
- add CPU OPP table
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Make use the new clock driver for RTL838X and RTL839x target devices. Of course
we will enable their primary consumer (cpufreq-dt) too. To be careful just set
the default governor to userspace. As we rely on SRAM activate that module too.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
A new clock driver makes more sense if it can be used from consumers
like cpufreq. Before we enable the driver we must tell the config that
the RTL838X and RTL839X targets allow CPU frequency changing.
Even though these targets currently rely on the CPU's internal R4K
timer, MIPS_EXTERNAL_TIMER is selected to allow for CPU frequency change
testing. The Realtek timers, which are clocked by the Lexra bus, still
need to be supported and used in order to provide correct wall times
when reclocking the CPU.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[add paragraph about MIPS_EXTERNAL_TIMER to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a new self-contained combined clock & platform driver that allows to
access the PLL hardware clocks of RTL83XX devices. Currently it provides
info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and
additionally allows to change the CPU clocks. Changing the clocks
multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and
is multithreading safe on the RTL839X. Even a cpufreq initiated change
of the CPU clock works fine. Loading the driver will add some meaningful
logging.
[0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz
[0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz,
MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove trailing whitespaces, C-style SPDX comments for ASM and headers]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Platform startup still "guesses" the CPU clock speed by DT fixed values.
If possible take clock rates from a to be developed driver and align to
MIPS generic platfom initialization code. Pack old behaviour into a
fallback function. We might get rid of that some day.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
General hardware info:
-------------------------------------------------------------------------------
D-Link DGS-1210-10MP is a switch with 8 ethernet ports and 2 SFP ports, all
ports Gbit capable. It is based on a RTL8380 SoC @ 500MHz, DRAM 128MB and
32MB flash. All ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 130W.
File info:
-------------------------------------------------------------------------------
The dgs-1210-10mp is very similar to dgs-1210-10p so I used that as a start.
rtl838x.mk:
- Removed lua-rs232 package since it was a leftover from the old rtl83xx-poe
package.
- Updated the soc to 8380.
- Specified device variant: F.
- Installed the new realtek-poe package.
rtl8380_d-link_dgs-1210-10mp.dts:
- Moved dgs-1210 family common parts and non PoE related ports on rtl8231
to the new device tree dtsi files.
Serial connection:
-------------------------------------------------------------------------------
The UART for the SoC (115200 8N1) is available close to the front panel next
to the LED/key card connector via unpopulated standard 0.1" pin header
marked j4. Pin1 is marked with arrow and square.
Pin 1: Vcc 3,3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
Installation with TFTP from u-boot
-------------------------------------------------------------------------------
I originally used the install procedure:
'OpenWrt installation using the TFTP method and serial console access' found
in the device wiki for the dgs-1210-16.
< https://openwrt.org/toh/d-link/dgs-1210-16_g1#openwrt_installation_using
_the_tftp_method_and_serial_console_access >
About the realtek-poe package
-------------------------------------------------------------------------------
The realtek-poe package is installed but there isn't any automatic PoE config
setting at this time so for now the PoE config must be edited manually.
Original OEM hardware/firmware data at first installation
-------------------------------------------------------------------------------
It has been installed, developed, and tested on a device with these OEM
hardware and firmware versions.
- U-boot: 2011.12.(2.1.5.67086)-Candidate1 (Jun 22 2020 - 15:03:58)
- Boot version: 1.01.001
- Firmware version: 6.20.007
- Hardware version: F1
Things to be done when support are developed
-------------------------------------------------------------------------------
- realtek-poe has been included in OpenWrt but the automatic config handling
has not been solved yet so in the future there will probably be some minor
updates for this device to handle the poe config.
- LED link_act and poe are per function supposed to be connected to the PoE
system.
But some software development is also needed to make this LED work and
shift the LED array between act and poe indication and to shift the mode
lights with mode key.
- LED poe_max should probably be used as straight forward error output from
the realtek-poe package error handling. But no code has been written for
this.
- SFP is currently not hot pluggable. Development is under progress to get
working I2C communication with SFP and have them hot pluggable.
When any device in the dgs-1210 family gets this working, I expect it
should be possible to implement the same solution in this device.
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
[Capitalisation of abbreviations, DEVICE_VARIANT and update filenames,
device compatibles on single line]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
I have collected the known information from the dts files we have.
After that I made a new device tree that should work for this whole D-Link
switch family.
This device tree is based on modules where you first select which SoC group
the device belongs to. Then you include the GPIO dtsi file depending on what
hardware your device has, see examples below.
This tree is also expandable for more hardware,
see the part 'Future expansion possibilities' further down.
-------------------------------------------------------------------------------
The device tree now looks like this:
----------------
| rtl838x.dtsi | // Note 1.
----------------
|
|
---------------------------------------
| rtl838x_d-link_dgs-1210_common.dtsi | // Note 2.
---------------------------------------
|
| --------------
|-------| device.dts | // Note 3.
| --------------
|
-------------------------------------
| rtl83xx_d-link_dgs-1210_gpio.dtsi | // Note 4.
-------------------------------------
|
| --------------
|-------| device.dts | // Note 5.
--------------
Note 1; Included in rtl838x_d-link_dgs-1210_common.dtsi.
Note 2; SoC level information and memory mapping. Choose which one to include
in the device dts.
Note 3; At this point dgs-1210-16 will come out here.
Note 4; In this dtsi only common board hardware based on the rtl8231 is found.
No PoE based hardware in this dtsi.
In this dtsi there is no <#include> to above *_common.dtsi.
Note 5; Device dts with only rtl8231 based hardware without PoE will come out
here.
-------------------------------------------------------------------------------
How to set up in dts file:
The device dts will have one of these two <#include> alternatives.
This alternative includes only common features:
<#include "rtl838x_d-link_dgs-1210_common.dtsi">
This alternative includes common and the rtl8231 GPIO (no PoE) features:
<#include "rtl838x_d-link_dgs-1210_common.dtsi">
<#include "rtl83xx_d-link_dgs-1210_gpio.dtsi">
-------------------------------------------------------------------------------
Implementation:
Finally, I also implemented this new family device tree on the current
supported devices:
dgs-1210-10p
dgs-1210-16
dgs-1210-20
dgs-1210-28
The implementation for the dgs-1210-10p is different. I have removed the
information from the rtl8382_d-link_dgs-1210-10p.dts that is already present
in rtl838x_d-link_dgs-1210_common.dtsi.
Since the rest isn't officially probed in the device dts I do not want to
include the rtl83xx_d-link_dgs-1210_gpio.dtsi with dgs-1210-10p.dts.
Since I don't have these devices to test on I have built the original firmware
for each one of these devices before this change and saved the dtb file and
then compared the original dtb file with the dtb file built with this new
device tree.
-------------------------------------------------------------------------------
Future expansion possibilities:
In parallel with the rtl838x_d-link_dgs-1210_common.dtsi in the tree map
we can make a rtl839x_d-link_dgs-1210_common.dtsi to use the rtl839x.dtsi if
the need arises with more devices based on rtl839x soc.
When we have more PoE devices so the hardware map for these gets more clear
we can make a rtl83xx_d-link_dgs-1210_poe.dtsi below
the rtl83xx_d-link_dgs-1210_gpio.dtsi in the tree map.
I looked at the port and switch setup to see if it could be moved to the dtsi.
I decided not to touch this part now. The reason was that there isn't really
any meaningful way this could be shared between the devices.
The only thing in common over the family is the 8+2sfp ports on the
dgs-1210-10xx device.
And then there is the hot plug SFP and I2C ports that aren’t implemented
on any device. So maybe when we see the whole port map for the family
then maybe the ports can be moved to a *_common.dtsi but I don't think it is
the right moment for that now.
Signed-off-by: Daniel Groth <flygarn12@gmail.com>
[Capitalisation of abbreviations and 'D-Link']
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add support for the TP-Link SG2008P switch. This is an RTL8380 based
switch with 802.3af one the first four ports.
Specifications:
---------------
* SoC: Realtek RTL8380M
* Flash: 32 MiB SPI flash (Vendor varies)
* RAM: 256 MiB (Vendor varies)
* Ethernet: 8x 10/100/1000 Mbps with PoE on 4 ports
* Buttons: 1x "Reset" button on front panel
* Power: 53.5V DC barrel jack
* UART: 1x serial header, unpopulated
* PoE: 1x TI TPS23861 I2C PoE controller
Works:
------
- (8) RJ-45 ethernet ports
- Switch functions
- System LED
Not yet enabled:
----------------
- Power-over-Ethernet (driver works, but doesn't enable "auto" mode)
- PoE, Link/Act, PoE max and System LEDs
Install via web interface:
-------------------------
Not supported at this time.
Install via serial console/tftp:
--------------------------------
The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.
The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.
Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWRT:
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
Power on device, and stop boot by pressing any key.
Once the shell is active:
1. Ground out the CLK (pin 16) of the ROM (U7)
2. Select option "3. Start"
3. Bootloader notes that "The kernel has been damaged!"
4. Release CLK as sson as bootloader thinks image is corrupted.
5. Bootloader enters automatic recovery -- details printed on console
6. Watch as the bootloader flashes and boots OpenWRT.
Blind install via tftp:
-----------------------
This method works when it's not feasible to install a serial header.
Prepare a tftp server with:
1. server address: 192.168.0.146
2. the image as: "uImage.img"
3. Watch network traffic (tcpdump or wireshark works)
4. Power on the device.
5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U7)
6. When 192.168.0.30 makes tftp requests, release pin 16
7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The root overlay is mounted on the "rootfs_data" partition. This comes
at the end of the firmware image, courtesy of mtdsplit. There is very
little space left (About 1MB), which can fill up rapidly.
The "firmware" and "firmware2" partitions are part of the bootloader
dual firmware logic. They should contain independent, valid uImages.
This leaves "jffs2-cfg" (mtd3) and "jffs2-log" (mtd4) as candidates.
mtd3 is about 13.7 MB and is used by the vendor firmware to store
configuration settings. It is only erased by vendor firmware during a
factory reset. By naming this partition "rootfs_data", it becomes the
root overlay, providing significantly more room. Even with mtdsplit
wanting to create a "rootfs_data" on the firmware partition, mtd3 is
used as the overlay.
Rename "jffs2-cfg" to "rootfs_data", and profit from the extra space.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The original commit for the GS110TP was missing ports 9 and 10. These
are provided by an external RTL8214C phy, for which no support was
available at the time. Now that this phy is supported, add the missing
entries to enable all device ports.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The function `ucidef_set_poe` receives a list of ports to add to the PoE array.
Since switches have many ports the varibale `lan_list` is passed instead of
writing every single lan port. However, this list includes partly SFP ports
which are unrelated to PoE.
This commits adds the option to add a third parameter to manually exclide
interfaces, usually the last two.
Signed-off-by: Paul Spooren <mail@aparcar.org>
[Replace glob by regex to be more specific about matching characters]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
All targets expect the malta target already activate the CONFIG_GPIOLIB
option. Move it to generic kernel configuration and also activate it for
malta.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Panasonic Switch-M48eG PN28480K is a 48 + 4 port gigabit switch, based on
RTL8393M.
Specification:
- SoC : Realtek RTL8393M
- RAM : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x48 + 2
- port 1-40 : TP, RTL8218B x5
- port 41-48 : RTL8218FB
- port 41-44: TP
- port 45-48: TP/SFP (Combo)
- LEDs/Keys : 7x / 1x
- UART : RS-232 port on the front panel (connector: RJ-45)
- 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
- 9600n8
- Power : 100-240 VAC, 50/60 Hz, 0.5 A
- Plug : IEC 60320-C13
- Stock OS : VxWorks based
Flash instruction using initramfs image:
1. Prepare the TFTP server with the IP address 192.168.1.111
2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
the TFTP directory
3. Download the official upgrading firmware (ex: pn28480k_v30000.rom)
and place it to the TFTP directory
4. Boot M48eG and interrupt the U-Boot with Ctrl + C keys
5. Execute the following commands and boot with the OpenWrt initramfs
image
rtk network on
tftpboot 0x81000000
bootm
6. Backup mtdblock files to the computer by scp or anything and reboot
7. Interrupt the U-Boot and execute the following commands to re-create
filesystem in the flash
ffsmount c:/
ffsfmt c:/
this step takes a long time, about ~ 4 mins
8. Execute the following commands to put the official images to the
filesystem
updatert <official image>
example:
updatert pn28480k_v30000.rom
this step takes about ~ 40 secs
9. Set the environment variables of the U-Boot by the following commands
setenv loadaddr 0xb4e00000
setenv bootcmd 'sleep 10; bootm;'
saveenv
'sleep 10;' is required as dummy to execute 'bootm' command correctly
10: Download the OpenWrt initramfs image and boot with it
tftpboot 0x81000000 0101A8C0.img
bootm
11: On the initramfs image, download the sysupgrade image and perform
sysupgrade with it
sysupgrade <imagename>
12: Wait ~ 120 seconds to complete flashing
Known Issues:
- 4x SFP ports are provided as combo ports by the RTL8218FB chip, but the
phy driver has no support for it. Currently, only TP ports work by the
RTL8218B support.
Note:
- "Switch-M48eG" is a model name, and "PN28480K" is a model number.
Switch-M48eG has an another (old) model number ("PN28480"), it's not a
Realtek based hardware.
- Switch-M48eG has a "POWER" LED (Green), but it's not connected to any
GPIO pin.
- U-Boot checks the runtime images in the flash when booting and fails
to execute "bootcmd" variable if the images are not existing.
- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
firmware and it includes the stock images, configuration files and
checksum files. It's unknown format, can't be managed on the OpenWrt.
To get the enough space for OpenWrt, move the filesystem to the head
of "fs_reserved" partition by execution of "ffsfmt" and "updatert".
- A GPIO pin on PCA9539 is used for resetting external RTL8218B phys and
RTL8218FB phy.
This should be specified as "reset-gpios" property in MDIO node, but
the current configuration of RTL8218B phy in the driver seems to be
incomplete and RTL8218FB won't be configured on RTL8218D support.
So, ethernet ports on these phys will be broken after hard-resetting.
At the moment, configure this pin as gpio-hog to avoid breaking by
resetting.
- This model has 2x Microchip TCN75A thermal sensors. Linux Kernel
supports TCN75 chip on lm75 driver, but no support for TCN75'A'
variant.
At the moment, use TCN75 support for the chips instead.
Back to the stock firmware:
1. Delete "loadaddr" variable and set "bootcmd" to the original value
on U-Boot:
setenv loadaddr
setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;'
on OpenWrt:
fw_setenv loadaddr
fw_setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;'
2. Perform reset or reboot
on U-Boot:
reset
on OpenWrt:
reboot
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The system status LED on Panasonic Switch-M48eG PN28480K is connected to
a PCA9539PW. To use the LED as a status LED of OpenWrt while booting,
enable the pca953x driver and built-in to the kernel.
Also enable CONFIG_GPIO_PCA953X_IRQ to use interrupt via RTL83xx GPIO.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Panasonic Switch-M24eG PN28240K is a 24 + 2 port gigabit switch, based on
RTL8382M.
Specification:
- SoC : Realtek RTL8382M
- RAM : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x24 + 2
- port 1-8 : TP, RTL8218B
- port 9-16 : TP, RTL8218B (SoC)
- port 17-24 : RTL8218FB
- port 17-22: TP
- port 23-24: TP/SFP (Combo)
- LEDs/Keys : 7x / 1x
- UART : RS-232 port on the front panel (connector: RJ-45)
- 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
- 9600n8
- Power : 100-240 VAC, 50/60 Hz, 0.5 A
- Plug : IEC 60320-C13
- Stock OS : VxWorks based
Flash instruction using initramfs image:
1. Prepare the TFTP server with the IP address 192.168.1.111
2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
the TFTP directory
3. Download the official upgrading firmware (ex: pn28240k_v30000.rom)
and place it to the TFTP directory
4. Boot M24eG and interrupt the U-Boot with Ctrl + C keys
5. Execute the following commands and boot with the OpenWrt initramfs
image
rtk network on
tftpboot 0x81000000
bootm
6. Backup mtdblock files to the computer by scp or anything and reboot
7. Interrupt the U-Boot and execute the following commands to re-create
filesystem in the flash
ffsmount c:/
ffsfmt c:/
this step takes a long time, about ~ 4 mins
8. Execute the following commands to put the official images to the
filesystem
updatert <official image>
example:
updatert pn28240k_v30000.rom
this step takes about ~ 40 secs
9. Set the environment variables of the U-Boot by the following commands
setenv loadaddr 0xb4e00000
setenv bootcmd bootm
saveenv
10: Download the OpenWrt initramfs image and boot with it
tftpboot 0x81000000 0101A8C0.img
bootm
11: On the initramfs image, download the sysupgrade image and perform
sysupgrade with it
sysupgrade <imagename>
12: Wait ~ 120 seconds to complete flashing
Known Issues:
- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
phy driver has no support for it. Currently, only TP ports work by the
RTL8218D support.
Note:
- "Switch-M24eG" is a model name, and "PN28240K" is a model number.
Switch-M24eG has an another (old) model number ("PN28240"), it's not a
Realtek based hardware.
- Switch-M24eG has a "POWER" LED (Green), but it's not connected to any
GPIO pin.
- U-Boot checks the runtime images in the flash when booting and fails
to execute "bootcmd" variable if the images are not existing.
- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
firmware and it includes the stock images, configuration files and
checksum files. It's unknown format, can't be managed on the OpenWrt.
To get the enough space for OpenWrt, move the filesystem to the head
of "fs_reserved" partition by execution of "ffsfmt" and "updatert".
- A GPIO pin on PCA9539 is used for resetting external RTL8218B phy and
RTL8218FB phy.
This should be specified as "reset-gpios" property in MDIO node, but
the current configuration of RTL8218B phy in the phy driver seems to
be incomplete and RTL8218FB won't be configured on RTL8218D support.
So, ethernet ports on these phys will be broken after hard-resetting.
At the moment, configure this pin as gpio-hog to avoid breaking by
resetting.
Back to the stock firmware:
1. Delete "loadaddr" variable and set "bootcmd" to the original value
on U-Boot:
setenv loadaddr
setenv bootcmd 'bootm 0x81000000'
on OpenWrt:
fw_setenv loadaddr
fw_setenv bootcmd 'bootm 0x81000000'
2. Perform reset or reboot
on U-Boot:
reset
on OpenWrt:
reboot
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Panasonic Switch-M16eG PN28160K is a 16 + 2 port gigabit switch, based on
RTL8382M.
Specification:
- SoC : Realtek RTL8382M
- RAM : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x16 + 2
- port 1-8 : TP, RTL8218B (SoC)
- port 9-16 : RTL8218FB
- port 9-14: TP
- port 15-16: TP/SFP (Combo)
- LEDs/Keys : 7x / 1x
- UART : RS-232 port on the front panel (connector: RJ-45)
- 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
- 9600n8
- Power : 100-240 VAC, 50/60 Hz, 0.5 A
- Plug : IEC 60320-C13
- Stock OS : VxWorks based
Flash instruction using initramfs image:
1. Prepare the TFTP server with the IP address 192.168.1.111
2. Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
the TFTP directory
3. Download the official upgrading firmware (ex: pn28160k_v30003.rom)
and place it to the TFTP directory
4. Boot M16eG and interrupt the U-Boot with Ctrl + C keys
5. Execute the following commands and boot with the OpenWrt initramfs
image
rtk network on
tftpboot 0x81000000
bootm
6. Backup mtdblock files to the computer by scp or anything and reboot
7. Interrupt the U-Boot and execute the following commands to re-create
filesystem in the flash
ffsmount c:/
ffsfmt c:/
this step takes a long time, about ~ 4 mins
8. Execute the following commands to put the official images to the
filesystem
updatert <official image>
example:
updatert pn28160k_v30003.rom
this step takes about ~ 40 secs
9. Set the environment variables of the U-Boot by the following commands
setenv loadaddr 0xb4e00000
setenv bootcmd bootm
saveenv
10: Download the OpenWrt initramfs image and boot with it
tftpboot 0x81000000 0101A8C0.img
bootm
11: On the initramfs image, download the sysupgrade image and perform
sysupgrade with it
sysupgrade <imagename>
12: Wait ~ 120 seconds to complete flashing
Known Issues:
- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
phy driver has no support for it. Currently, only TP ports work by the
RTL8218D support.
Note:
- "Switch-M16eG" is a model name, and "PN28160K" is a model number.
Switch-M16eG has an another (old) model number ("PN28160"), it's not a
Realtek based hardware.
- Switch-M16eG has a "POWER" LED (Green), but it's not connected to any
GPIO pin.
- U-Boot checks the runtime images in the flash when booting and fails
to execute "bootcmd" variable if the images are not existing.
- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
firmware and it includes the stock images, configuration files and
checksum files. It's unknown format, can't be managed on the OpenWrt.
To get the enough space for OpenWrt, move the filesystem to the head
of "fs_reserved" partition by execution of "ffsfmt" and "updatert".
- A GPIO pin on PCA9539 is used for resetting external RTL8218FB phy.
This should be specified as "reset-gpios" property in MDIO node, but
RTL8218FB won't be configured on RTL8218D support in the phy driver.
So, ethernet ports on the phy will be broken after hard-resetting.
At the moment, configure this pin as gpio-hog to avoid breaking by
resetting.
Back to the stock firmware:
1. Delete "loadaddr" variable and set "bootcmd" to the original value
on U-Boot:
setenv loadaddr
setenv bootcmd 'bootm 0x81000000'
on OpenWrt:
fw_setenv loadaddr
fw_setenv bootcmd 'bootm 0x81000000'
2. Perform reset or reboot
on U-Boot:
reset
on OpenWrt:
reboot
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
As the symbol RTL930x shows, the bool enables the RTL930x platform, not
the RTL839x one.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
(slightly changed commit subject)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Support for HPE 1920 images depends on two non-existent tools (mkh3cimg
and mkh3cvfs) from the in the firmware-utils package. Revert commit
f2f09bc002 ("realtek: add support for HPE 1920 series") until support
for these tools is merged and made available in OpenWrt.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware information:
---------------------
- HPE 1920-8G:
- RTL8380 SoC
- 8 Gigabit RJ45 ports (built-in RTL8218B)
- 2 SFP ports (built-in SerDes)
- HPE 1920-16G / HPE 1920-24G (same board):
- RTL8382 SoC
- 16/24 Gigabit RJ45 ports (built-in RTL8218B, 1/2 external RTL8218D)
- 4 SFP ports (external RTL8214FC)
- Common:
- RJ45 RS232 port on front panel
- 32 MiB NOR Flash
- 128 MiB DDR3 DRAM
- PT7A7514 watchdog
Booting initramfs image:
------------------------
- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
connect the server to a switch port.
- Connect to the console port of the device and enter the extended
boot menu by typing Ctrl+B when prompted.
- Choose the menu option "<3> Enter Ethernet SubMenu".
- Set network parameters via the option "<5> Modify Ethernet Parameter".
Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
can be left blank, it is not required for booting from RAM). Note that
the configuration is saved on flash, so it only needs to be done once.
- Select "<1> Download Application Program To SDRAM And Run".
Initial installation:
---------------------
- Boot an initramfs image as described above, then use sysupgrade to
install OpenWrt permanently. After initial installation, the
bootloader needs to be configured to load the correct image file
- Enter the extended boot menu again and choose "<4> File Control",
then select "<2> Set Application File type".
- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
use the option "<1> +Main" to select it as boot image.
- Choose "<0> Exit To Main Menu" and then "<1> Boot System".
NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Don't use udelay to allow other kernel tasks to execute if the kernel
has been built without preemption. Also determine the timeout based on
jiffies instead of loop iterations.
This is especially important on devices containing a watchdog with a
short timeout. Without this change, the watchdog is not serviced during
PHY patching which can take multiple seconds.
Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Probe the SFP module during PHY initialization and implement
insertion/removal handlers to automatically configure the media type
of the respective port.
Suggested-by: Birger Koblitz <git@birger-koblitz.de>
Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Move RTL8214FC power configuration to newly created suspend and resume
methods. A media change now only results in power configuration if the
PHY is not suspended, to avoid powering up a port when the interface is
currently not up.
While at it, remove the rtl8380 prefix from function names, as this is
actually not SoC-specific.
Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Toggle power on the individual PHY instead of the package. Otherwise
a media change always toggles power on the first port, and not the one
that is being configured.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
We are close to provide enduser friendly OpenWrt images for DGS-1210
switches that do not need serial console. Nevertheless a small bit is
missing. We cannot switch back to the vendor partition or initiate a
download of a vendor firmware image. To issue this from inside OpenWrt
we need write access to U-Boot environment.
Case 1: Switch back to secondary (vendor) image
> fw_setenv bootcmd run addargs\; bootm 0xb4e80000
> fw_setenv image /dev/mtdblock7
> reboot
Case 2: Issue D-Link Network Assistant based download on next reboot.
This is a combination of some vendor specific protocol (DDP) and a
TFTP download afterwards.
> fw_setenv bootstop on
> reboot
Allow these commands by opening up u-boot-env for write access.
Tested on DGS-1210-20.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The interrupt controller in the internal GPIO peripheral will sometimes
generate spurious interrupts. If these are not properly acknowledged, the
system will be held busy until reboot. These spurious interrupts are identified
by the fact that there is no system IRQ number associated, since the interrupt
line was never allocated. Although most prevalent on RTL839x, RTL838x SoCs have
also displayed this behaviour.
Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> # DGS-1210-52
Reported-by: Birger Koblitz <mail@birger-koblitz.de> # Netgear GS724TP v2
Reported-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-16G
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Destination switch ports for outgoing frame can range from 0 to
CPU_PORT-1.
Refactor the code to only generate egress frame CPU headers when a valid
destination port number is available, and make the code a bit more
consistent between different switch generations. Change the dest_port
argument's type to 'unsigned int', since only positive values are valid.
This fixes the issue where egress frames on switch port 0 did not
receive a VLAN tag, because they are sent out without a CPU header.
Also fixes a potential issue with invalid (negative) egress port numbers
on RTL93xx switches.
Reported-by: Arınç ÜNAL <arinc.unal@xeront.com>
Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.
Current code for RTL83xx forces the passed priority value to be
positive, by always masking it to the lower bits, resulting in the
priority always being set and enabled. RTL93xx code doesn't even check
the value and unconditionally assigns the (32 bit) value to the (5 bit)
QID field without masking.
Fix priority assignment by only setting the AS_QID/AS_PRI flag when a
valid value is passed, and properly mask the value to not overflow the
QID/PRI field.
For RTL839x, also assign the priority to the right part of the frame
header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36
and 37-39. The means they should be assigned to the third 16 bit value,
containing bits 32-47.
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The flag to enable L2 address learning on egress frames is in CPU header
bit 40, with bit 0 being the leftmost bit of the header. This
corresponds to BIT(7) in the third 16-bit value of the header.
Correctly set L2LEARNING by fixing the off-by-one error.
Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The flag to enable the outgoing port mask is in CPU header bit 43, with
bit 0 being the leftmost bit of the header. This corresponds to BIT(4)
in the third 16-bit value of the header.
Correctly set AS_DPM by fixing the off-by-one error.
Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
setup.c unconditionally sets the sys-led mode (blinking rate) to a
permanent high output. This may cause issues when a board expects this
pin to toggle periodically, e.g. when hooked up to an external watchdog.
If the sys-led peripheral is used to control an LED, the mux should be
configured to use the pin as GPIO0, allowing for better control as a
GPIO LED.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The devicetree for the ZyXEL XGS1250-12 was missing the description of
the front panel LED labeled "PWR SYS". Let's add it so it can be
controlled by the user.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Like for RTL838x devices, add a pinctrl-single node to manage the
sys-led/gpio0 mux, and allow using the pin as GPIO.
Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Not all devices using the gpio0/sys-led pin as a GPIO, configure the
pinmux. Add the necessary pinctrl properties to these devices to ensure
the pin is set up for use as GPIO.
Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
During upload of firmware images the WebUI and CLI patch process
extracts a version information from the uploaded file and stores it
onto the jffs2 partition. To be precise it is written into the
flash.txt or flash2.txt files depending on the selected target image.
This data is not used anywhere else. The current OpenWrt factory
image misses this label. Therefore version information shows only
garbage. Fix this.
Before:
DGS-1210-20> show firmware information
IMAGE ONE:
Version : xfo/QE~WQD"A\Scxq...
Size : 5505185 Bytes
After:
DGS-1210-20> show firmware information
IMAGE ONE:
Version : OpenWrt
Size : 5505200 Bytes
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Currently we build factory images only for DGS-1210-28 model. Relax
that constraint and take care about all models. Tested on DGS-1210-20
and should work on other models too because of common flash layout.
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
From now on we will insert CAMEO tags into sysupgrade images for
DGS-1210 devices. This will make the "OS:...FAILED" and "FS:...FAILED"
messages go away.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
GPIO 1 on the RTL8231 is used to force the PoE MCU to disable power
outputs. It is not used by any driver, but if accidentally set low,
PoE outputs are disabled. This situation is hard to debug, and
requires knowledge of the Broadcom PoE protocol used by the MCU.
To prevent this situation, hog it as an output high. This is
consistent with the ZyXel GS1900 series handles it.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
DGS-1210 switches support dual image, with each image composed of a
kernel and a rootfs partition. For image1, kernel and rootfs are in
sequence. The current OpenWrt image (written using a serial console),
uses those partitions together as the firmware partition, ignoring the
partition division. The current OEM u-boot fails to validate image1 but
it will only trigger firmware recovery if both image1 and image2 fail,
and it does not switch the boot image in case one of them fails the
check.
The OEM factory image is composed of concatenated blocks of data, each
one prefixed with a 0x40-byte cameo header. A normal OEM firmware will
have two of these blocks (kernel, rootfs). The OEM firmware only checks
the header before writing unconditionally the data (except the header)
to the correspoding partition.
The OpenWrt factory image mimics the OEM image by cutting the
kernel+rootfs firmware at the exact size of the OEM kernel partition
and packing it as "the kernel partition" and the rest of the kernel and
the rootfs as "the rootfs partition". It will only work if written to
image1 because image2 has a sysinfo partition between kernel2 and
rootfs2, cutting the kernel code in the middle.
Steps to install:
1) switch to image2 (containing an OEM image), using web or these CLI
commands:
- config firmware image_id 2 boot_up
- reboot
2) flash the factory_image1.bin to image1. OEM web (v6.30.016)
is crashing for any upload (ssh keys, firmware), even applying OEM
firmwares. These CLI commands can upload a new firmware to the other
image location (not used to boot):
- download firmware_fromTFTP <tftpserver> factory_image1.bin
- config firmware image_id 1 boot_up
- reboot
To debrick the device, you'll need serial access. If you want to
recover to an OpenWrt, you can replay the serial installation
instructions. For returning to the original firmware, press ESC during
the boot to trigger the emergency firmware recovery procedure. After
that, use D-Link Network Assistant v2.0.2.4 to flash a new firmware.
The device documentation does describe that holding RESET for 12s
trigger the firmware recovery. However, the latest shipped U-Boot
"2011.12.(2.1.5.67086)-Candidate1" from "Aug 24 2021 - 17:33:09" cannot
trigger that from a cold boot. In fact, any U-Boot procedure that relies
on the RESET button, like reset settings, will only work if started from
a running original firmware. That, in practice, cancels the benefit of
having two images and a firmware recovery procedure (if you are not
consider dual-booting OpenWrt).
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Setting up DSA bond silently fails if mode is not 802.3ad. Add log message
to fix it. As we are already here harmonize all logging messages in the
add/delete functions.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The SFP cages 9F and 10F share the same SCL line. Currently, there
isn't a good way to model this. Thus, only one SFP port can be fully
supported.
Cage 10F is fully supported with an I2C bus and sfp handle. Linux
automatically handles enabling or disabling the TX laser.
Cage 9F is only parially supported, without the sfp handle. The SDA
line is hogged as an input, so that it remains high. SCL transitions
sould not affect modules connected to this cage. The default value of
the tx-disable line is high (active). It is exported as a gpio, but
the laser is off by default. To enable the laser:
echo 0 > /sys/class/gpio/sff-p9-tx-disable/value
Thus, both modules can be used for networking, but only 10F will be
able to detect and identify a plugged in SFP module.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add support for the Engenius EWS2910P PoE switch. This is an RTL8380
based switch with two SFP slots, and PoE 802.3af one every RJ-45 port.
The specs say 802.3af, but the vendor firmware configures the PSE for
a budget of 31W, indicating 802.3at support.
Specifications:
---------------
* SoC: Realtek RTL8380M
* Flash: 32 MiB SPI flash Macronix MX25L25635E
* RAM: 256 MiB (As reported by bootloader)
* Ethernet: 16x 10/100/1000 Mbps with PoE
2x SFP slots
* Buttons: 1 "Reset" button on front panel
1 "LED mode: button on front panel
1 "On/Off" Toggle switch on the back
* Power: 48V-54V DC barrel jack
* UART: 1 serial header (JP1) with populated 2.54mm pitch header
Labeled GRTV for ground, rx, tx, and 3.3V respectively
* PoE: 1 STM ST32F100 microcontroller
2 BCM59111 PSE chips
Works:
------
- (8) RJ-45 ethernet ports
- Switch functions
- LEDs and buttons
Not yet enabled:
----------------
- SFP ports (will be enabled in a subsequent change)
- Power-over-Ethernet (requires realtek-poe package)
Install via web interface:
-------------------------
The factory firmware will accept and flash the initramfs image. It is
recommended to flash to "Partition 0". Flashing to "Partition 1" is
not supported at this point.
The factory web GUI will show the following warning:
" Warning: The firmware version is v0.00.00-c0.0.00
The firmware image you are uploading is older than the current
firmware of the switch. The device will reset back to default
settings. Are you sure you want to proceed?"
This is expected when flashing OpenWrt. After the initramfs image
boots, flash the -sysupgrade using either the commandline or LuCI.
Install via serial console/tftp:
--------------------------------
The u-boot firmware will not stop the boot, regardless of which key is
pressed. To access the u-boot console, ground out the CLK (pin 16) of
the ROM (U22) when u-boot is reading the linux image. If timed
correctly, the image CRC will fail, and u-boot will drop to a shell:
> rtk network on
> setenv ipaddr <address of tftp server>
> tftp $(freemem) <name-of-initramfs-image.bin>
> bootm
Then flash the -sysupgrade using either the commandline or luci.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[gpio-led node names, OpenWrt and LuCI capitalization in commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
This is now built-in, enable so it won't propagate on target configs.
Link: https://lkml.org/lkml/2022/1/3/168
Fixes: 79e7a2552e ("kernel: bump 5.15 to 5.15.44")
Fixes: 0ca93670693b ("kernel: bump 5.10 to 5.10.119")
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
(Link to Kernel's commit taht made it built-in,
CRYPTO_LIB_BLAKE2S[_ARM|_X86] as it's selectable, 5.10 backport)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
The Netgear GS3xx devices do not properly initialise the port LEDs during
startup unless the boot command in U-Boot is changed. Making the U-Boot
env partition writable allows this modification to be done from within
OpenWrt by calling "fw_setenv bootcmd rtk network on\; boota".
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Make the u-boot environment partition for the NETGEAR
GS108T v3 and GS110TPP writable (they share a DTS), so
the values can be manipulated from userspace.
See https://forum.openwrt.org/t/57875/1567 for a real
world example.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
The Netgear GS108Tv3 is already supported by OpenWrt, but is missing LED
support. After OpenWrt installation, all LEDs are off which makes the
installation quite confusing.
This enables support for the green/amber power LED to give feedback
about the current status.
This is basically just a verbatim copy of commit c4927747d2 ("realtek:
add support for power LED on Netgear GS308Tv1").
Please note that both LEDs are wired up in an anti-parallel fashion,
which means that only one of both LEDs/colors can be switched on at the
same time. If both LEDs/colors are switched on simultanously, the LED
goes dark.
Tested-by: Pascal Ernster <git@hardfalcon.net>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
[add title to commit reference]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Hardware specification
----------------------
* RTL8382M SoC, 1 MIPS 4KEc core @ 500MHz
* 128MB DRAM
* 32MB NOR Flash
* 16 x 10/100/1000BASE-T ports
- Internal PHY with 8 ports (RTL8218B)
- External PHY with 8 ports (RTL8218B)
* 4 x Gigabit RJ45/SFP Combo ports
- External PHY with 4 SFP ports (RTL8214FC)
* Power LED
* Reset button on front panel
* UART (115200 8N1) via unpopulated standard 0.1" pin header marked J6
UART pinout
-----------
[o]ooo|J6
| ||`------ GND
| |`------- RX
| `-------- TX
`---------- Vcc (3V3)
Boot initramfs image from U-Boot
--------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl838x-d-link_dgs-1210-20-initramfs-kernel.bin` command
5. Boot the image with `bootm` command
To install, upload the sysupgrade image to the OEM webpage or sysupgrade
from the system running from initramfs image.
It has been developed and tested on device with F1 revision.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct initramfs image name]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
