Now the rtl931x target has real devices that need to be built. Remove the
source-only flag to make the images available.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20172
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Plasma Cloud ESX28 Switch is a 24 + 4 port multi-GBit switch with
24x 10/100/1000/2500BaseT Ethernet ports and 4x SFP+ module slot.
Hardware:
- RTL9312C SoC
- Macronix MX25L25645G (32MB flash)
- 512MB DDR3 SDRAM
- RTL8231 GPIO extender to control the port LEDs
- 6x RTL8224 4x 10m/100m/1/2.5 Gigabit PHY
- SFP+ 4x 10GBit slot
The switch is powered directly via AC.
The external RS232 serial connector (RJ45, Cisco pinout) can be used to
access the terminal. Serial connection is via 115200 baud, 8N1.
A reset button is accessible through a hole in the front panel.
Installation
------------
* The device can be flashed by using sysupgrade command. Either from the
original vendor firmware or using an initramfs (see "Debug")
* Connect serial on front panel. Connection parameters: 115200 8N1
* The image must be copied using scp to /tmp of the device
scp openwrt-realtek-rtl931x-plasmacloud_esx28-squashfs-sysupgrade.bin root@[IP address of the device]:/tmp/
* start sysupgrade without saving the original vendor configuration
sysupgrade -n /tmp/openwrt-realtek-rtl931x-plasmacloud_esx28-squashfs-sysupgrade.bin
Installation via u-boot
-----------------------
If you have an TFTP server connected to the switch, it is possible to
directly install the device using the factory image from u-boot
# setup networking and IP of TFP server
rtk network on
setenv ipaddr 10.100.100.99
setenv serverip 10.100.100.20
# get factory image
tftp 0x84000000 factory.bin
# erase firmware partitions
sf probe 0
sf erase 0x5e0000 0x1a20000
# write firmware to both partitions
sf write ${fileaddr} 0x5e0000 ${filesize}
sf write ${fileaddr} 0x12f0000 ${filesize}
# adjust the boot commands
setenv bootargs "mtdparts=spi0.0:768k(u-boot),64k(u-boot-env),64k(u-boot-env2),5120k(reserved),13376k(inactive),13376k(firmware2)"
setenv bootcmd "rtk init; bootm 0xb52f0000"
# restart
reset
Debug
-----
* Connect serial on front panel. Connection parameters: 115200 8N1.
* A tftp server is required, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enter passwords: "1234" or "plasmapsx"
* Enable network:
rtk network on
* Change ip address of device:
setenv ipaddr 192.168.1.6
* Download initramfs from TFTP server:
tftpboot 0x84000000 192.168.1.111:openwrt-realtek-rtl931x-plasmacloud_esx28-initramfs-kernel.bin
* Boot loaded file:
bootm 0x84000000
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20172
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Plasma Cloud PSX28 Switch is a 24 + 4 port multi-GBit switch with
24x 10/100/1000/2500BaseT Ethernet ports and 4x SFP+ module slot.
Hardware:
- RTL9312C SoC
- Macronix MX25L25645G (32MB flash)
- 512MB DDR3 SDRAM
- RTL8231 GPIO extender to control the port LEDs
- 6x RTL8224 4x 10m/100m/1/2.5 Gigabit PHY
- SFP+ 4x 10GBit slot
- RTL8239 POE++ PSE controller with frontend MCU
The switch is powered directly via AC.
The external RS232 serial connector (RJ45, Cisco pinout) can be used to
access the terminal. Serial connection is via 115200 baud, 8N1.
A reset button is accessible through a hole in the front panel.
Installation
------------
* The device can be flashed by using sysupgrade command. Either from the
original vendor firmware or using an initramfs (see "Debug")
* Connect serial on front panel. Connection parameters: 115200 8N1
* The image must be copied using scp to /tmp of the device
scp openwrt-realtek-rtl931x-plasmacloud_psx28-squashfs-sysupgrade.bin root@[IP address of the device]:/tmp/
* start sysupgrade without saving the original vendor configuration
sysupgrade -n /tmp/openwrt-realtek-rtl931x-plasmacloud_psx28-squashfs-sysupgrade.bin
Installation via u-boot
-----------------------
If you have an TFTP server connected to the switch, it is possible to
directly install the device using the factory image from u-boot
# setup networking and IP of TFP server
rtk network on
setenv ipaddr 10.100.100.99
setenv serverip 10.100.100.20
# get factory image
tftp 0x84000000 factory.bin
# erase firmware partitions
sf probe 0
sf erase 0x5e0000 0x1a20000
# write firmware to both partitions
sf write ${fileaddr} 0x5e0000 ${filesize}
sf write ${fileaddr} 0x12f0000 ${filesize}
# adjust the boot commands
setenv bootargs "mtdparts=spi0.0:768k(u-boot),64k(u-boot-env),64k(u-boot-env2),5120k(reserved),13376k(inactive),13376k(firmware2)"
setenv bootcmd "rtk init; bootm 0xb52f0000"
# restart
reset
Debug
-----
* Connect serial on front panel. Connection parameters: 115200 8N1.
* A tftp server is required, tftpd-hpa works well.
* Power the device, at U-Boot start rapidly hit Esc key to stop autoboot
* Enter passwords: "1234" or "plasmapsx"
* Enable network:
rtk network on
* Change ip address of device:
setenv ipaddr 192.168.1.6
* Download initramfs from TFTP server:
tftpboot 0x84000000 192.168.1.111:openwrt-realtek-rtl931x-plasmacloud_psx28-initramfs-kernel.bin
* Boot loaded file:
bootm 0x84000000
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20172
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
To be able to read out the ethaddr from the u-boot environment for MAC
address configuration, it is required to also enable the NVMEM layout
parsing code for the U-Boot env layout.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20172
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
OpenWrt buildroot will compile all dtbs defined in target to
$(KDIR)/image-$(DEVICE_DTS).dtb, so make use of it to allow us
debug and use external dtbs easier without patching kernel Makefile.
This also fixes commit 5c724939c3 which forgot to update DTS_DIR
in KERNEL variable.
Fixes: 5c724939c3 ("rockchip: add DEVICE_DTS_DIR definition")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20286
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
If transmissions are done outside of the DSA switch (directly from the CPU
port), the STP state must not block the transmission. Otherwise, STP frames
are not correctly submitted and the STP frames cannot correctly detect
loops before switching a port in the forwarding state.
The same applies for the LLDP frames. These must be submitted independent
of the STP state to identify neighbors or configure POE limits.
It is not necessary to filter specific destination mac addresses because
the transmission was done outside the bridge/switch in the first place. The
transmission is therefore forced.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <sven@narfation.org>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/20184
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL930X and RTL931X SoCs support port-based, flow-based, and
RSPAN-based mirroring. Like for other SoCs from the realtek target, only
the port based port mirroring can be exposed using Linux's tc subsystem.
The port_mirror_add() implementation was updated with the following
considerations for RTL93xx SoCs:
* mirrored packets must pass through the TX pipeline of the mirroring
port, so they are subject to configuration such as VLAN tagging,
remarking, and EVC
* when a packet hits both source ports (SPM) and destination port (DPM) of
a mirror group, the egress port traffic will be mirrored
The port_mirror_del() function doesn't require any modifications.
Signed-off-by: Sharadanand Karanjkar <sk@simonwunderlich.de>
Co-developed-by: Sven Eckelmann <se@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20264
Signed-off-by: Robert Marko <robimarko@gmail.com>
Instead of using a lot of if-else blocks in the port mirror code, provide
SoC specific function which calculates the SoC specific portions. The
generic part of the port mirroring code can then simply operate on the
calculated register addresses and values.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20264
Signed-off-by: Robert Marko <robimarko@gmail.com>
The FIT loadaddr on RK3308/RK3566/RK3568/RK358x is 0x02000000
instead of 0x02080000, while on RK3576 it's 0x42000000, which is
quite different from the former SoCs and incompatible with current
kernel loadaddr value.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/20041
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Replace the pending I2C backport patches for RTL93XX added in
44655c97bb with the upstreamed variants. The patches have been accepted
upstream in the meantime and are included in v6.17 or v6.18.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20273
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL931x has next to its SPI flash controller a SPI master interface. It
is connected to
* SPI_CS#[1,0]: AH22 , AK22 (aka: GPIO 12, 11)
* SPI_CLK: AL23 (aka: GPIO 8)
* SPI_MISO: AM23 (aka: GPIO 9)
* SPI_MOSI: AL22 (aka: GPIO 10)
It is not the same as the SPI flash controller which uses pins:
* SPI_CS#[1,0]: B24, A24
* SPI_SCLK: A23
* SPI_SDI/SIO0: B21
* SPO_SDO_SIO1: B21
* SPI_SIO2: A22
* SPI_SIO3: B22
* SPI_RSTN: B23
As shown above, the SPI master controller shares its pin with GPIO 8, 9,
10, 11, 12. In some upcoming devices (like the Plasma Cloud PSX28/ESX28),
they will be used for SFP cage signaling. These pins must therefore be
switched manually to the GPIO mode.
The SPI_CTRL0 register provides all necessary configuration to enforce the
GPIO mode of the pins. And until more requirements (and a correct driver)
for the SPI master controller arise, it is therefore possible to use
pinctrl-single to configure it using the devicetree.
Previously the ethernet driver did configure the SPI master controller for
31.25 MHz. It is unknown for which kind of device this was originally made
and what was actually connected there. But this manual write to the
register conflicts potentially with the write of the pinctrl driver to the
same register. Luckily, we don't need this SPI speed configuration in the
ethernet driver. Still, to allow this device an easy migration, the
`spi0-31mhz` configuration was already prepared.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20263
Signed-off-by: Robert Marko <robimarko@gmail.com>
The RTL8224 used by Plasma Cloud PSX8/PSX10 is not using USXGMII but
USXGMII 10G-QXGMII mode. The correct phy-mode string for this is
"10g-qxgmii".
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20239
Signed-off-by: Robert Marko <robimarko@gmail.com>
The current SerDes implementation for RTL931x handles 10G-QXGMII via the
"usxgmii" PHY mode. This is not 100% correct because it is not a single
port with 10G (max) but 4 ports with 2.5G each.
To allow setting of the "10g-qxgmii" phy mode, just change the code for now
to use the same codepaths as USXGMII. This has to be cleaned up further
during the SerDes driver rewrites.
Suggested-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20239
Signed-off-by: Robert Marko <robimarko@gmail.com>
The Plasma Cloud PSX28 and ESX28 are using RTL8224 as ethernet PHY. This
phy works perfectly fine on PSX8/PSX10 (RTL930x) but failed to establish a link
on rtl931x because the upstream realtek phy driver was not enabled.
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20239
Signed-off-by: Robert Marko <robimarko@gmail.com>
Deprecated. Replaced with nvmem.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20176
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20176
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20176
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20176
Signed-off-by: Robert Marko <robimarko@gmail.com>
Upstream will get support for the Realtek ECC engine with 6.18.
To make use of this in Openwrt
- backport upstream patches
- change config so that ECC will be built for nand subtargets
- define ECC engine in RTL93xx DTS.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19746
Signed-off-by: Robert Marko <robimarko@gmail.com>
During testing, we discovered that when adding a new offload FDB rule
on certain VLANs and then delete it, does not work as expected.
Steps to Reproduce:
* Create VLAN 4094 on the port lan1:
bridge vlan add vid 4094 dev lan1 pvid
* Add a new FDB entry on port lan1 for VLAN 4094:
bridge fdb add 00:01:02:22:33:44 dev lan1 vlan 4094 master permanent
* Delete the new FDB entry on port lan1 for VLAN4094
bridge fdb del 00:01:02:22:33:44 dev lan1 vlan 4094 master permanent
Root Cause:
The failure occurs because the hash_msb flag is not set correctly
based on the VLAN ID when adding a new L2 entry.
Signed-off-by: Issam Hamdi <ih@simonwunderlich.de>
Signed-off-by: Sven Eckelmann <se@simonwunderlich.de>
Link: https://github.com/openwrt/openwrt/pull/20183
Signed-off-by: Robert Marko <robimarko@gmail.com>
Align GS1900-10HP dts with other realtek devices to reduce the risk of device
specific regressions with the upcoming driver cleanup/rewrite.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/20228
Signed-off-by: Robert Marko <robimarko@gmail.com>
Parse the pcs-handle property regardless of phy-handle
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/20228
Signed-off-by: Robert Marko <robimarko@gmail.com>
Check if the uploaded image matches the version of RouterBOOT before
proceeding with sysupgrade on MikroTik devices with NOR flash.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
RouterBOOT v7 for NOR devices does not support the historic yaffs
"kernel" ELF boot method.
Generate a compatible kernel
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
RouterBOOT v7 for NOR devices does not support the historic yaffs
"kernel" ELF boot method.
Generate a compatible kernel
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
RouterBOOT v7 for NOR devices does not support the historic yaffs
"kernel" ELF boot method.
Generate a compatible kernel
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
Add missing syscon compatible for scuclk node.
Fix the unit-address of the scuclk node.
This fixes the pcs driver error:
airoha-pcs 1fa08000.pcs: probe with driver airoha-pcs failed with error -22
airoha-pcs 1fa09000.pcs: probe with driver airoha-pcs failed with error -22
Fixes: c3d70b1 ("airoha: en7581: Add support for external PHY")
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/20190
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The pinctrl driver for airoha was expecting a function name that was
not a string, but was passed one. Removing #string fixed this issue.
Fixes: c5b12fc ("airoha: Introduce support for Airoha AN7583 SoC")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/20190
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This patch already exists in generic/backport-6.12.
Fixes: 122135b ("airoha: an7581: add support for kernel 6.12")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/20190
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
All devices under airoha use dts directory under the target,
so update the default DEVICE_DTS_DIR. Also set the default
DEVICE_DTS based on the SoC name for non-dev boards.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://github.com/openwrt/openwrt/pull/20190
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Add support for swapping the Serdes TX line on RTL8261N PHYs.
This is used on an Arcadyan Mozart board where the Serdes TX is swapped
on the PHY (instead of on the Soc) to permit support of SFP module by
using toggling the integrated MUX.
Link: https://github.com/openwrt/openwrt/pull/20227
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Update with make kernel_oldconfig CONFIG_TARGET=target. Also disable
CONFIG_POSIX_MQUEUE, as it's available in the OpenWrt configuration.
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
This is an automatically generated commit which aids following Kernel patch
history, as git will see the move and copy as a rename thus defeating the
purpose.
For the original discussion see:
https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Userspace handling is deprecated.
Also convert custom LED to one handled by ath9k.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20112
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Upstream DTS in 6.12 contains many changes from our copy.
Move the remaining diff, which is LED aliases, USB ports and partition
labels into a patch and drop the full copy.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/19786
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Upstream DTS in 6.12 is almost identical to our copy.
Move the partition label change into a patch and drop the full copy.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/19786
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Upstream DTS in 6.12 is almost identical to our copy.
Move LED and partition tweaks into a patch and drop the full copy.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/19786
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Upstream DTS is almost identical to our copy. Move network aliases and
phy-mode into a patch and drop the full copy.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/19786
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Upstream DTS in 6.12 is almost identical to our copy.
The only non-trivial difference is ethernet aliases. Move this change
into a patch and drop the full copy.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/19786
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
All changes to the DTS have been applied upstream, remove our DTS copy.
This change effectively drops the workaround for the 2500Base-x
interface which was broken until kernel 5.15 and removes redundant
address-/size-cells.
Signed-off-by: Stefan Kalscheuer <stefan@stklcode.de>
Link: https://github.com/openwrt/openwrt/pull/19786
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Point the driver to the precal section of the emmc "factory" partition.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/20154
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Replace the hotplug script with nvmem now that loading data from emmc
partitions is supported.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/20154
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Avoids the occacial lost race, where VAPs are created before the hotplug
script has updated the phy mac address.
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Link: https://github.com/openwrt/openwrt/pull/20154
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Prior to the deletion of the old IXP4xx codebase we supported
Actiontec MI424WR A, C and D.
This brings back the support using the upstream device trees
from Linux.
Link: https://github.com/openwrt/openwrt/pull/20066
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This corrects the WRV54G device tree and adds patches for
MI424WR alongh with GPIO MMIO support for the same.
Link: https://github.com/openwrt/openwrt/pull/20066
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add missing bluetooth support btif in dts.
Signed-off-by: Elwin Huang <s09289728096@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20181
Signed-off-by: Robert Marko <robimarko@gmail.com>
Introduce initial support for Airoha AN7583 SoC and add all the required
patch for basic functionality of the SoC.
Airoha AN7583 is based on Airoha EN7581 SoC with some major changes on
the PHY handling and Serdes. It can be see as a lower spec of EN7581
with modern and simplified implementations.
All the patch are sent upstream and are pending revision. Support for
PCIe and USB will come later as soon as DT structure is accepted
upstream.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
To correctly init the CPUFreq driver, CPUFREQ_DT is needed. While at it
also enable CPU HOTPLUG kconfig to support hotplug of secondary CPU.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This add a pending version of the Airoha PCS driver to add support for
External PHY. The Airoha PCS driver will receive some minor modification
once we the PCS subsystem will be defined upstream.
Add all the required node for GDM2 and GDM4 and enable the PCS config.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
There are SFP modules which only work if auto-negotiation is disabled,
like some "OEM SFP-2.5G-T" modules. This also seems to be necessary for
RTL8226/RTL8221B PHYs when using 2500Base-X.
However, currently, it is always enabled, so add support for configuring
it to make these SFP modules and PHYs work.
This also adds locking which should be useful for future extension of
the PCS driver.
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
Link: https://github.com/openwrt/openwrt/pull/19518
Signed-off-by: Robert Marko <robimarko@gmail.com>
Now that MDIO and DSA driver only look for pcs-handle drop all
usages of the sds property.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20148
Signed-off-by: Robert Marko <robimarko@gmail.com>
In the Realtek dts the pcs-handle property at the switch port is the
successor of the sds property at the phy. Rearrange the MDIO and DSA
driver so they always look at the new attribute.
Remark! This code can be dropped completely if the new PCS driver
is fully featured. But this will take some time.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20148
Signed-off-by: Robert Marko <robimarko@gmail.com>
Switch Airoha targets to 6.12 and drop 6.6 support.
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20137
Signed-off-by: Robert Marko <robimarko@gmail.com>
en7523 compilation on 6.12 fails with a no prototype warning. Fix this
by declaring max_transfer_size and transfer_one_message static.
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20138
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Zyxel labels their switch revisions A1, B1, ... and not v1, v2, ...
Rename the supported device to A1 to make it clear this is the only
known compatible hardware revision.
Also add a compatible for seamless upgrade.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20118
Signed-off-by: Robert Marko <robimarko@gmail.com>
Zyxel labels their switch revisions A1, B1, ... and not v1, v2, ...
Rename the devices as such in OpenWrt to match the labels. Of note:
the first (A1) revision is never labeled as such on the label, just
in the web UI. Provide compatibles for seamless sysupgrade.
For a recent overview of Zyxel GS1900 series revisions, see the
table linked in https://forum.openwrt.org/t//57875/3874.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20118
Signed-off-by: Robert Marko <robimarko@gmail.com>
Zyxel labels their switch revisions A1, B1, ... and not v1, v2, ...
Rename the devices as such in OpenWrt to match the labels. Of note:
the first (A1) revision is never labeled as such on the label, just
in the web UI. Provide compatibles for seamless sysupgrade.
For a recent overview of Zyxel GS1900 series revisions, see the
table linked in https://forum.openwrt.org/t//57875/3874.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20118
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17344
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling is deprecated.
Move the mac address patch to 10_fix_wifi_mac.
This uses an AR9287, which uses a smaller size for its calibration.
The PCI ID is also wrong.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19864
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit fixes stability issues on certain RAX3000Me devices. Some
devices has DDR3 RAM which don't able to work reliably at 2133 MHz
and require special BL2 (1866 MHz RAM freq).
Fixes: https://github.com/openwrt/openwrt/issues/20046
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20059
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This patch has already been accepted and landed in 6.17.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20132
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
No functional changes intended.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20131
Signed-off-by: Robert Marko <robimarko@gmail.com>
No functional changes intended.
Fixes warning:
/linux/arch/arm64/boot/dts/airoha/en7581-gemtek-w1700k.dtb: i2c1@1fbf8100 (mediatek,mt7621-i2c): status: 'oneOf' conditional failed, one must be fixed:
['disable'] is not of type 'object'
'disable' is not one of ['okay', 'disabled', 'reserved', 'fail', 'fail-needs-probe']
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20131
Signed-off-by: Robert Marko <robimarko@gmail.com>
Now that there is a dedicated PCS driver remove the old functions
from the DSA driver and make use of the new ones.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20129
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
For all switch ports where the assigned SerDes is known, add the new
pcs-handle to the dts. Leave the existing <sds> assignments to the
PHYs as is because the driver has not yet been updated.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20111
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit adds support for Buffalo WSR-6000AX8 and AX8P models.
Hardware
--------
SOC: MediaTek MT7986B
RAM: 512MB
FLASH: 128MB SPI-NAND (Winbond)
WIFI 2.4G: (Embedded in SOC) b/g/n/ax, MIMO 4x4
WIFI 5G: (Embedded in SOC) a/n/ac/ax, MIMO 4x4
ETHERNET: 2.5GbE MaxLinear GPY211C (eth1: WAN)
ETHERNET: MediaTek MT7531AE 3xGbE (eth0: LAN1, LAN2, LAN3)
UART: 3.3V 115200 8N1
Serial(UART) Pin Layout
-----------------------
+-------+-------+-------+-------+
J4 | RX | TX | GND |(3.3V) |
+-------+-------+-------+-------+
(Bottom Side)
MAC Address Table
-----------------
lan1-3: board_data 0x4(text)
eth1/WAN: board_data 0x4(text)
WIFI 2.4G: lan1 + 2
WIFI 5G: lan1 + 9
Installation
------------
1. Set up a TFTP server with the IP address "192.168.11.2".
2. Rename the OpenWrt initramfs image to "linux.ubi-recovery" and place it
in the TFTP server's root directory.
3. While holding down the AOSS button, power on the WSR-6000AX8 (or AX8P).
4. The device will automatically download the initramfs image
from the TFTP server and boot into it.
5. Once booted, run "sysupgrade -n" using the OpenWrt sysupgrade image
to complete the installation.
Recovery
--------
1. Decrypt the official firmware image using "buffalo-enc".
example:
$ buffalo-enc -d -i wsr_6000ax8_jp_100 -o wsr_6000ax8_jp_100.dec \
-l -O 0xc8
2. Run "sysupgrade -F -n" with the decrypted image.
Signed-off-by: Shin Sato <shin.sugar.ssyysy2021@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/13107
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Specification :
- SOC : Mediatek MT7981B (1.3GHz)
- RAM : 256MB
- Flash : 16MB SPI NOR
- Ports : 4 LAN (1G) & 1 WAN (1G)
- WIFI : MediaTek dual-band WiFi 6
- 2.4 GHz : b/g/n/ax, MIMO 2x2
- 5 GHz : a/n/ac/ax, MIMO 2x2
- Buttons : Reset & WPS/Mesh
- LEDS : WAN (Green), Status (Red & Blue)
- Power : 12V1A
Install via OEM web ui:
Upload the sysupgrade image to firmware upgrade page on OEM web ui
Install via recovery / revert to stock firmware:
1. Unplug from power
2. Download the Sysupgrade (for openwrt installation) or OEM Factory image (for revert to stock firmware)
3. Set your computer ethernet IP to 192.168.1.X, subnet 255.255.255.0 (X=your chosen ip number ranging from 2-254)
4. Press and hold reset button while turn on / plug power adapter to the router. Wait untill ALL LAN green LED turn on, then release the reset button.
5. Plug the LAN cable from your computer into LAN 1 port then open web browser, and type in the address column : 192.168.1.1
6. Upload the sysupgrade / oem factory image
7. Wait until the router finished flashing (the router will reboot)
8. Set ethernet ip to dhcp
9. Open 192.168.1.1 (for openwrt install) / 192.168.0.1 (for OEM firmware)
Signed-off-by: Ari Kurniawan <noobhek@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20035
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Now that we have a board file, add calibration variant for TP-Link
Archer C60 v1 and add ipq-wifi package for it.
Signed-off-by: Christoph Krapp <achterin@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19993
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This fixes a previous commit breaking setting the MAC address for the
wifi devices.
Fixes: 9ed4d27fbf ("mediatek: filogic: fix 5G MAC address for Zyxel EX5601")
Link: https://github.com/openwrt/openwrt/pull/20100
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Until now the the SerDes configuration is realized with helper functions
scattered around the DSA and PHY driver. Give them a new home as a PCS
driver.
The target design is as follows:
- dsa driver manages switch
- pcs driver manages SerDes on high level (this commit)
- mdio driver manages SerDes on low level
This driver adds the high level SerDes access via PCS. It makes use of
the low level mdio SerDes driver to access the registers.
Remark: This initial version provides exactly all phylink_pcs_ops that
are currently part of the DSA driver. So this can be swapped in one of
the next commits as a drop in replacement. To make use of it something
like this is needed:
...
ports = of_get_child_by_name(node, "ethernet-ports");
if (!ports)
return -EINVAL;
for_each_available_child_of_node(ports, port) {
pcs_node = of_parse_phandle(port, "pcs-handle", 0);
of_property_read_u32(port, "reg", &port_nr)) {
priv->pcs[port_nr] = rtpcs_create(dev, pcs_node, port_nr);
}
...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20075
Signed-off-by: Robert Marko <robimarko@gmail.com>
In the future the PCS & DSA drivers will lookup the SerDes of a
switch port via pcs-handle (like upstream does). Provide a macro
that allows to expand the existing port definitions. To link a
SerDes to port simply do
Either in short form:
replace SWITCH_PORT(0, 1, qsgmii)
with SWITCH_PORT_SDS(0, 1, 3, qsgmii) (Link to SerDes 3)
Or in long form:
port@24 {
reg = <24>;
label = "lan25";
pcs-handle = <&serdes4>; (Link to SerDes 4)
phy-handle = <&phy24>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
};
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20075
Signed-off-by: Robert Marko <robimarko@gmail.com>
The fixes for the dying timers were finally accepted upstream.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20097
Signed-off-by: Robert Marko <robimarko@gmail.com>
Instead of having two LED entries that supposedly control the same
thing, set the pin properly.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18905
Signed-off-by: Robert Marko <robimarko@gmail.com>
of_gpio.h is deprecated in upstream Linux and may be removed soon. Get
ahead of things and remove it. Most of these drivers already use the
gpiod API.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20076
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is a smart door lock device equipped with OpenWrt 14.07 OEM
modified version Qdwrt
The OEM has closed down, This commit is intended to maximize the
remaining value of these devices. It can flash OpenWrt to become
an AP
Specification:
- SoC: MediaTek MT7628NN
- Flash: 8 MB
- RAM: 64 MB
- Power: DC 5V - 25V
- Ethernet: 1 x RJ45 (10/100 Mbps)
- Wireless radio: 802.11n 2.4g-only
- On-Board LED:
Status 1: GPIO/43 active-low
Status 2: GPIO/44 active-low
Power: AlwaysOn
- Button:
WPS / RESET: GPIO/14 active-low
- Bluetooth: CC2541 via UART1 (ttyS1) and GPIO/26-29
- RFID: MF RC522 on I2C@28
- RTC: DS1339 on I2C@68
- Shell (via CON1 cable)
- LED (Swipe card area):
- Green GPIO/3 active-high
- Red GPIO/11 active-high
- Matrix keypad: (active-low)
GPIO/20 GPIO/21 GPIO/19 (Rows)
GPIO/24 1 2 3
GPIO/25 4 5 6
GPIO/22 7 8 9
GPIO/23 BACK 0 ENTER
(Cols)
- UART: 1 x UART on PCB - 57600 8N1
- GPIO Relay: GPIO/42 active-high
- GPIO Buzzer: GPIO/15 active-high
Warning:
The original firmware does not use the device tree.
This device tree is written based on the content of /sys/devices/platform
and has been tested
Note:
- On the device, matrix keypad rows actually are columns, and the columns actually are rows
- The key code of the CLEAR key of the matrix keypad is BACK in the original firmware.
Issue:
- No drivers in mainline kernel for RFID and Bluetooth.
Flash Instruction:
Using SSH/Telnet:
1. Connect the board to the computer via RJ45 Ethernet
2. Login 10.10.10.1 with root password "szqdingnet123" (SSH Port 22, Telnet Port 9900)
3. Download openwrt firmware on the computer.
4. Setup a http server on computer. And use wget download openwrt firmware from computer
5. Use command "mtd -r write openwrt-ramips-mt76x8-qding_qc202-squashfs-sysupgrade.bin firmware"
to flash
Using U-Boot WebUI:
1. Configure PC with a static IP address 10.10.10.2/24.
2. Open http://10.10.10.1
3. Use "mkqdimg -B qc202 -f openwrt-ramips-mt76x8-qding_qc202-squashfs-sysupgrade.bin" to
make image.
4. Upload factory.bin via U-Boot WebUI.
Original Firmware Dump / More details:
https://blog.gov.cooking/archives/research-qianding-smart-locker-and-flash.html
Original U-Boot firmware image tools:
https://gitlab.com/CoiaPrant/mkqdimg
Signed-off-by: Coia Prant <coiaprant@gmail.com>
Tested-by: Coia Prant <coiaprant@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/17471
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently following warnings are given
dts/rtl930x.dtsi:166.4-23: Warning (reg_format):
/switchcore@1b000000/i2c@36c:reg: property has invalid length
(8 bytes) (#address-cells == 2, #size-cells == 1)
Obviously default address-cells size is fixed to 64 bit. Align
with upstream and override address size to 32 bit.
Suggested-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20091
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add node to support the second UART node controller in IPQ5018.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/20090
Signed-off-by: Robert Marko <robimarko@gmail.com>
Specification:
SoC: Mediatek MT7981BA
RAM: 512 MB DDR4 RAM
Flash: Winbond W25N01GV 128 MB SPI-NAND (dual boot on OEM)
WiFi: MT7976CN DBDC AX
Switch: MediaTek MT7531AE (3x LAN Gigabit ports) + Internal Gbe Phy (1x WAN Gigabit port)
GPIO: 4x LED (power, internet, fn, wifi), 2x buttons (wps, reset), 1x switch (mesh)
UART Interface:
Pins: VCC, TX, RX, NC, GND
Settings: 115200, 8N1
Flashing via TFTP:
1. Connect your PC and router to the first LAN port, configure PC interface using IP 192.168.1.2, mask 255.255.255.0
2. Save the factory image of the OpenWRT firmware, renamed to KN-3711_recovery.bin, on the TFTP server
3. Hold the reset button and power up the device
4. Keep the button pressed until the status LED starts blinking
Signed-off-by: Vladimir Epifantsev <volatilefield@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19633
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The EN751221 has an XHCI that is compatible with MT7621.
While there is setup logic in the vendor code for both
EN751221 and MT7621, but MT7621 does not use it in mainline
or OpenWRT, and it appears to work correctly with EN751221.
Include SCSI / Mass Storage because many EcoNet devices
contain a builtin USB SD-Card reader.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/20050
[Remove usb storage kmod from smartfiber_xp8421-b]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The baud rate control on Airoha does not function properly. This
patch enables the inactive code responsible for this. The UART2
baud rate is correct. HSUART3 operates at twice the requested
baud rate. The same problem exists in the current code, so this
doesn't introduce any regression. Support for baud rates higher
than 460800 is still required. This will be added in the future.
Tested on Gemtek W1700k. UART2 and HSUART3 are working fine.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/20049
Signed-off-by: Robert Marko <robimarko@gmail.com>
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.47
No patches needed to be rebased.
Build system: x86/64
Build-tested: Build-tested: flogic/xiaomi_redmi-router-ax6000-ubootmod, x86/64-glibc
Run-tested: flogic/xiaomi_redmi-router-ax6000-ubootmod, x86/64-glibc
Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/20003
Signed-off-by: Robert Marko <robimarko@gmail.com>
The driver makes its own ath9k LED which handles everything.
Simplifies DTS slightly.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20023
Signed-off-by: Robert Marko <robimarko@gmail.com>
Userspace handling for this is deprecated.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20023
Signed-off-by: Robert Marko <robimarko@gmail.com>
The upcoming PCS driver will lookup the SerDes mdio bus via
of_mdio_find_bus() and the devicetree. This is only possible
with proper registration via devm_of_mdiobus_register().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20078
Signed-off-by: Robert Marko <robimarko@gmail.com>
No need two write a dedicated 1:1 mapping function and link that
for all the targets except RTL931x. Combine everything into a generic
helper and reduce the configuration structure.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20078
Signed-off-by: Robert Marko <robimarko@gmail.com>
The new SerDes mdio driver produces the following compilation
error in non-debug builds.
drivers/net/mdio/mdio-realtek-otto-serdes.c:72:12:
error: 'rtsds_sds_to_mmd' defined but not used [-Werror=unused-function]
72 | static int rtsds_sds_to_mmd(int sds_page, int sds_regnum)
| ^~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Move the function into the debug section.
Fixes: 7a7ee72c4d ("realtek: mdio: add SerDes driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20078
Signed-off-by: Robert Marko <robimarko@gmail.com>
In first commit I successfully bring WAN port into ethernet switch,
without realizing that I was using custom bootloader. But if using
original bootloader it do not works. WAN port in original bootloader
is tied to using its own GMAC.
This fix is made so this firmware will be compatible with orignal
bootloader, so the user can directly flash from stock firmware without
changing anything.
Signed-off-by: Roy H <roy@altbytes.com>
Link: https://github.com/openwrt/openwrt/pull/20039
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Despite having the same tplink.dtsi file, there are differences in wifi
Move wifi nodes out of dtsi to make it clear what the chipset is and
what calibration size should be used.
While at it, change to use led-sources to simplify LED setup.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20024
Signed-off-by: Robert Marko <robimarko@gmail.com>
Until now the SerDes access is realized with some helper functions
in the mdio bus. These were moved around a lot and had no real home.
End that temporary solution to move them where they belong.
The target design for the different Realtek drivers is as follows:
- dsa driver manages switch
- pcs driver manages SerDes on high level (to be developed)
- mdio driver manages SerDes on low level (this commit)
This driver adds the low level SerDes access via mdio. For debugging
purposes the user can interact with the SerDes in different ways.
First, there is a debug interface in
/sys/kernel/debug/realtek_otto_serdes/serdes.X/registers.
With that a dump of all registers can be shown.
> cat /sys/kernel/debug/realtek_otto_serdes/serdes.4/registers
Back SDS 4: 00 01 02 03 04 05 06 07 08
SDS : 0C03 0F00 7060 7106 074D 0EBF 0F0F 0359 5248
SDS_EXT : 0000 0000 85FA 8C6D 5CCC 0000 20D8 0003 79AA
...
Second, one can read/write registers via the mmd functions of the
mdio command line tool. Important to know: The registers are accessed
on the vendor specific MDIO_MMD_VEND1 device address (=30). Additionally
the SerDes page and register are concatenated into the the mmd register.
Top 8 bits are SerDes page and bottom 8 bits are SerDEs register.
E.g.
- mmd 0x0206 : SerDes page 0x02, SerDes register 0x06
- mmd 0x041f : SerDes page 0x04, SerDes register 0x1f
Read register 0x02 on page 0x03 of SerDes 0
> mdio realtek-serdes-mdio mmd 0:30 raw 0x0302
Write register 0x12 on page 0x02 of SerDes 1
> mdio realtek-serdes-mdio mmd 1:30 raw 0x0212 0x2222
For now this driver is only defined in the devicetree and activated
in the kernel build. There is no current consumer but at least
the debugging interface is available. Cleanup of the currently used
SerDes functions will come later.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20062
Signed-off-by: Robert Marko <robimarko@gmail.com>
There is some open coding in the ethernet driver. Drop
that and use kernel helpers instead.
- Use napi_gro_receive() instead of local skb list
- Use skb_put_data() instead of skb_put() plus memcpy()
- Use netdev_alloc_skb_ip_align() instead of manual alignment
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20030
Signed-off-by: Robert Marko <robimarko@gmail.com>
Refresh patches 6.12 for airoha and econet
Fixes: 122135b964 ("airoha: an7581: add support for kernel 6.12")
Fixes: 73d0f92460 ("kernel: Add new platform EcoNet MIPS")
Signed-off-by: Leo Barsky <leobrsky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/20073
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed patch for adding the QUP3 I2C node.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/20070
Signed-off-by: Robert Marko <robimarko@gmail.com>
Enable kernel 6.12 as the testing kernel for airoha.
This first commit will largely maintain feature-parity with kernel 6.6.
DTS changes are backwards-compatible with kernel 6.6.
Tested to flash and boot on Gemtek W1700K (#17869).
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/19038
Signed-off-by: Robert Marko <robimarko@gmail.com>
This is an automatically generated commit.
When doing `git bisect`, consider `git bisect --skip`.
Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/19038
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use label MAC to set addresses for wireless interfaces
for Linksys MX4200v2 and MX4300.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18759
Signed-off-by: Robert Marko <robimarko@gmail.com>
ascii-env driver allows reading mac addresses directly from devinfo partition from dts level.
Additionally label mac address have been set.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/18759
Signed-off-by: Robert Marko <robimarko@gmail.com>
This adds the Vitesse VSC73xx DSA switch modules to the two
Gemini devices that have them.
Link: https://github.com/openwrt/openwrt/pull/20057
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Refresh patch which was accidentally without non-confrming style and
not matching line numbers.
Also add patch description by copying the description of the commit
in OpenWrt, so the patch can be applied using `git am` and is ready
for upstream submission.
Fixes: afcec128c5 ("mediatek: add support for trng on mt7988a")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use upstreamed patches for adding IPQ CMN PLL driver support and its
node and clocks to the DTS accordingly.
In addition, set clock-div and clock-mult properties instead of the
frequency itself for the XO board clock in all board files as it's
converted to a fixed factor clock.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed patch for adding the crypto nodes.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed patch for adding the PRNG node.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed patch for adding the SPI nand node.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed patch for adding driver support and the the mdio and phy
nodes.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use upstreamed patch for adding the tsens node.
Temperature sensors are enabled by default, therefore remove explicit
enablement in board files.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19890
Signed-off-by: Robert Marko <robimarko@gmail.com>
Converts the KS8995 "phy" driver to a proper DSA switch.
Currently the upstream only supports the "none" tag
but this is a good improvement already.
Make the old module depend on kernel 6.6 and the new
one depend on !6.6.
The Realtek RTL8261n patch needs to be refreshed
because of textual dependencies.
Realtek RTL838x DSA and phy patches also have textual
dependencies and need to be refreshed.
The Mediatek in-flight DSA patch and related patches
also need to be rebased and refreshed.
Link: https://github.com/openwrt/openwrt/pull/19970
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This change fixes the eeprom load failure while on boot
Signed-off-by: Rhnn Hur <hurrhnn@icmp.kr>
Link: https://github.com/openwrt/openwrt/pull/20044
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This addresses #9113 by adding up to 1MB padding after writing the
rootfs image. On boot mount_root will probe for existing filesystems
after the rootfs image data. Without overwriting the initial free
space left on the rootfs partition, OpenWrt might incorrectly detect
an exising filesystem and fails to mount it, resulting in a bricked
device as the overlayfs will not be mountend and settings will not be
available.
Fixes#9113.
Signed-off-by: Orne Brocaar <info@brocaar.com>
Link: https://github.com/openwrt/openwrt/pull/19997
Signed-off-by: Robert Marko <robimarko@gmail.com>
During SerDes rework the helper functions were temporarily
renamed to ..._new(). Fix the leftovers by
- giving the functions a new rtsds_ prefix nad
- dropping the _new appendix.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20034
Signed-off-by: Robert Marko <robimarko@gmail.com>
Specification
-------------
- SoC : MediaTek MT7986AV quad-core ARM Cortex-A53 2GHz
- RAM : DDR4 512Mbytes, Nanya Technology NT5AD256M16E4
- Flash : 128Mbytes NAND Flash, ESMT F50L1G41LB
- WLAN : MediaTek MT7976DAN, MediaTek MT7916AN, MediaTek MT7976AN
- 2.4GHz : b/g/n/ax, Multi User MIMO
- 5GHz : a/n/ac/ax, Multi User MIMO
- 6GHz : ax, Multi User MIMO
- Ethernet : 10/100/1000 Mbps x4, LAN (MediaTek MT7531AE)
10/100/1000/2500 Mbps x1, WAN (MaxLinear GPY211C0VC)
- UART : 1x4 pin header on PCB
- [J1] 3.3V, TX, RX, GND (115200, 8N1)
- Buttons : WPS, Reset
- Switches : Rfkill Slide Switch
- USB : 1x USB 3.0 (MediaTek MT7986AV peripheral)
- FAN : 1x Fan (off - slow - fast)
- LEDs : 1x Power (Blue)
1x CPU (Blue)
1x Wi-Fi 6GHz (Blue)
1x Wi-Fi 5GHz (Blue)
1x Wi-Fi 2.4GHz (Blue)
4x LAN activity (Blue)
1x WAN activity (Blue)
1x USB 3.0 (Blue)
- Power : 12VDC, 3.5A (Center positive polarity)
MAC address
-----------
+-----------+-------------------+------------------------+
| Interface | MAC | Algorithm |
+-----------+-------------------+------------------------+
| WLAN 2.4G | 58:86:94:xx:xx:xx | label1 |
| WLAN 5G | 5A:86:94:xx:xx:xx | label2 with LA Bit set |
| WLAN 6G | 5A:86:94:xx:xx:xx | label1 with LA Bit set |
| WAN | 58:86:94:xx:xx:xx | label1 + 1 |
| LAN | 58:86:94:xx:xx:xx | label1 + 3 |
+-----------+-------------------+------------------------+
The WLAN 2.4G MAC address (label1) was found in 'Factory' partition, 0xA0004
The WLAN 5G MAC address (label2) was found in 'Factory' partition, 0x4
Installation
------------
1. Download the OEM recovery software (ipTIME Firmware Wizard (11ac))
from the manufacturer's website
2. Download the *squashfs-factory.bin file from the OpenWrt website
3. Press a reset button, and power up the router (keep pressing the reset button)
4. Wait more than 10 seconds until the CPU LED stop blinking
5. Connect the router (LAN port) to the PC
6. Run the OEM recovery software and follow the instructions
7. Select the *squashfs-factory.bin file during the router recovery process
8. Wait for the router to boot from *squashfs-factory.bin
Note: The router will automatically reboot if no file is uploaded within
55 seconds.
Fan Control
------------
The fan speed is controlled by writing a value from 0 to 2 to the
`fan1_target` file.
```
cd /sys/devices/platform/gpio-fan/hwmon/hwmon2
echo '0' > fan1_target // off
echo '1' > fan1_target // slow
echo '2' > fan1_target // fast
```
Limitation: Enabling Wi-Fi 6E
----------
Wi-Fi 6E (6GHz) does not work out of the box on LuCI.
After installation, you need to configure a few settings in the `radio1`
and `default_radio1` sections of the `/etc/config/wireless`.
Once you have made these changes, you can enable and use Wi-Fi 6E.
In the `radio1` section, you need to add three common options:
- band: must be set to `6g`
- country: a valid country code for the 6GHz band
- channel: a preferrend scanning channel (PSC) for 6GHz
In the `default_radio1` section, you need to add the SSID and key:
- ssid: The public name of your Wi-Fi network
- key: The Wi-Fi password
- encryption: must be set to either `sae` for WPA3 or `owe` for OWE
(open network)
Example:
```
config wifi-device 'radio1'
...
option band '6g'
option country 'KR'
option channel '37'
...
config wifi-iface 'default_radio1'
...
option ssid 'my_wifi_6e_name'
option key 'my_strong_password1234'
option encryption 'sae'
...
```
Note: A list of all the 6GHz PSC channels:
```
5, 21, 37, 53, 69, 85, 101, 117, 133, 149, 165, 181, 197, 213, and 229
```
Limitation: Maximum Transmit Power
----------
The maximum transmit power is currently broken. In the drop-down menu,
you can only choose between "driver default" and "255 dBm (2147493647
mW)". There is currently no workaround for the issue. Please leave the
maximum transmit power set to "driver default".
Signed-off-by: Donghyun Ko <nyankosoftware@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19763
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add driver for hardware random number generator found in MT7981, MT7988
and MT7987. This gives us a fast source of high-quality random numbers
on those platforms.
root@OpenWrt:~# cat /dev/hwrng | rngtest -c 10000
rngtest 6.17
Copyright (c) 2004 by Henrique de Moraes Holschuh
This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
rngtest: starting FIPS tests...
rngtest: bits received from input: 200000032
rngtest: FIPS 140-2 successes: 9988
rngtest: FIPS 140-2 failures: 12
rngtest: FIPS 140-2(2001-10-10) Monobit: 2
rngtest: FIPS 140-2(2001-10-10) Poker: 0
rngtest: FIPS 140-2(2001-10-10) Runs: 4
rngtest: FIPS 140-2(2001-10-10) Long run: 6
rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
rngtest: input channel speed: (min=616.108; avg=11979.007; max=19531250.000)Kibits/s
rngtest: FIPS tests speed: (min=1.859; avg=82.116; max=83.656)Mibits/s
rngtest: Program run time: 18629928 microseconds
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
The kernel config accidentally contains CONFIG_UBIFS_FS_AUTHENTICATION
which select a number of other unnecessary components, remove them.
The target has at least two subtargets, only one is currently
implemented. Move the Device builds into a file for this subtarget.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/20027
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Now that HSGMII is not used any longer drop the patch
the invents this mode.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20002
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The only consumers of the Realtek HSGMII (2.5G SGMII) mode were
the RTL8226/RTL8221B PHYs. These have been converted to dynamic
SGMII/2500base-x mode switching. Drop the leftovers of the mode
implementation.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/20002
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The mdio controller got its own dts node with a dedicated bus node.
Until now it still searches the phy nodes in the ethernet node.
Change the driver so it searches the nodes at the right location.
For this to work move the phy nodes in all dts/dtsi over to the new
bus node. Use the following replacement rule:
Replace old full declaration
ðernet0 {
mdio-bus {
...
};
};
and old abbreviated declaration
&mdio {
...
};
simply with the new declaration
&mdio_bus0 {
...
};
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The mdio controller has now its own target specific device nodes. This
is much closer to upstream notation. Adapt the driver to make use of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Until now the mdio bus is a subnode of the ethernet device. This
coupling is different from upstream and wrong. Ethernet and mdio
are different devices. Additionally differentiate between mdio
controller and mdio bus. To make it clear:
- There is one mdio controller
- With up to 4 busses (on RTL93xx)
Prepare new mdio controller and bus nodes with SoC specific compatibles.
These will be used later when refactoring the mdio driver probing.
Remark! For now only define the first bus for the RTL93xx targets.
So the driver still relies on "rtl9300,smi-address = <x y>;". It will
need much more refactoring to get totally aligned with upstream.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19986
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
While converting the RTL931x SerDes code to the new frontend
access methods, the target specific workarounds where left in
place. The old functions were kept and the phy/sds mapping
was unchanged too. It is time to clean this up
- drop the old functions
- reuse the existing read/write logic
- harden the new functions
For now keep the function naming rtmdio_...__new() as is. This
will be changed in a future commit.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19973
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
They have the same 0x200 calibration size.
Added various compatible lines in various places to make it clear what
device we're talking about.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19863
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These devices use AR9285, which uses 1f8 as the calibration size, not
440 like newer chips do. Actually the driver mandates a minimum of 200.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19863
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The TP-Link Archer VR1200v (v2) is a low end DSL modem based on the
EcoNet EN751221 processor platform.
While it does have an unlocked bootloader, the factory upgrade feature
requires a cryptographic signature so flashing from the web UI is not
feasible.
The Archer VR1200v (v2) uses a dual-image layout. I have chosen to reuse
this to support dual-boot between OpenWRT and the factory firmware.
Flashing instructions (from bootloader):
Build and then locate the squashfs-sysupgrade.bin image file
Get the length of that file in hex: printf '%X\n' "$(stat -c%s the-file-squashfs-sysupgrade.bin)"
Connect to device with xmodem capability, e.g. picocom --send-cmd lsx -vv -b 115200 /dev/ttyUSB0
Switch device on and press a key within 3 seconds, you should get to a `bldr>` prompt
Type: xmdm 80020000 <file length hex>
Quickly start xmodem and send the file, in picocom that is ctrl+a ctrl+s <paste-the-file-name> enter If the transfer fails to start, wait 30 seconds to a minute for the bootloader prompt to return and then try the command again.
Once the transfer has completed successfully, type the following flash 80000 80020000 <file length hex>
Type `re` or simply restart the device to boot into OpenWRT
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/19021
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The SmartFiber XP8421-B is a fiber modem which is available for $20 online
and has 512MB of memory, 256MB of SPI NAND flash and 2 USB 2.0 ports in
addition to ethernet, wifi and XPON.
Because EcoNet is not currently producing evaluation boards, the XP8421-B
stands in as a convenient, low cost, off-the-shelf, representitive example
of the capabilities of the EN751221 econet processor. This is also the
example board that is included in the upstream Linux patchset.
The XP8421-B, and apparently many other devices of this platform, use a
dual-image layout. I have chosen to reuse this to support dual-boot between
OpenWRT and the factory firmware. Certain design decisions were made with
the goal of not overwriting data that is used by the factory OS.
This commit also introduces a utility for switching between OS_A and OS_B
which are used for OpenWRT and Factory OS respectively.
Flashing instructions (from bootloader):
Build and then locate the squashfs-tclinux.trx image file
Get the length of that file in hex: printf '%X\n' "$(stat -c%s the-file-squashfs-tclinux.trx)"
Connect to device with xmodem capability, e.g. picocom --send-cmd lsx -vv -b 115200 /dev/ttyUSB0
Switch device on and press a key within 3 seconds
Enter bootloader username and password: telecomadmin nE7jA%5m
Type: xmdm 80020000 <file length hex>
Quickly start xmodem and send the file, in picocom that is ctrl+a ctrl+s <paste-the-file-name> enter If the transfer fails to start, wait 30 seconds to a
minute for the bootloader prompt to return and then try the command again.
Once the transfer has completed successfully, type the following flash 80000 80020000 <file length hex>
Type go or simply restart the device to boot into OpenWRT
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/19021
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
EcoNet EN75xx is a big endian MIPS platform used in XPON (fiber),
DSL, and SIM (3g/4g) applications. Complete GPL vender SDKs exist
for this platform, but are based on Linux 2.6.
The bulk of this submission has already been accepted upstream:
https://patchwork.kernel.org/project/linux-mips/list/?series=960479&state=*
This platform uses a bootloader that is derived from old TrendChip
code. This bootloader implements a frustratingly complex Bad Block
Table which is implemented here in en75_bmt.c
This BMT is not upstreamed because it depends on mtk_bmt framework
which likewise is not upstreamed.
This BMT system rewrites block indexes in flash and if the bootloader
considers it to be corrupted, it will attempt to automatically rebuild
on boot. So without implementing the algorithm, you can't safely use
the disk at all.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://github.com/openwrt/openwrt/pull/19021
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware
--------
RockChip RK3568 ARM64 (4 cores)
1/2GB LPDDR4 RAM
2x 2500 Base-T (PCIe, r8125b)
1 LED (Power)
1 Button (Reset)
Micro-SD Slot
2x USB 3.0 Port
12V DC Jack
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card using
dd.
Tested-by: Francisco G Luna <frangonlun@gmail.com>
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19990
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Add labels wan and cpu for ethernet ports.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19968
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently 5G wireless interface MAC address is incorrect.
Fix by setting MAC address using Factory data.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19968
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Convert NWA50AX Pro to use NVMEM framework for wifi macaddr.
Also remove the unused macaddr@a.
Signed-off-by: Zhi-Jun You <hujy652@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/19982
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Convert NWA50AX Pro to use NVMEM framework for EEPROM/precal.
Signed-off-by: Zhi-Jun You <hujy652@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/19982
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These are already specified in DTS. Only thing missing is
label-mac-device.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19806
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Support in mt76 has existed for quite a while. Use it.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19806
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After trying to implement the gluon support for this device I ended up in a boot loop due to the usable amount of flash left. With this patch layout it uses the unused and empty flash space in the original partiton layout.
The version 3 of this device the RE365 share the same approach to have more usable space.
Signed-off-by: Steffen Förster <nemesis@chemnitz.freifunk.net>
Link: https://github.com/openwrt/openwrt/pull/18639
Signed-off-by: Sander Vanheule <sander@svanheule.net>
A lot of definitions in the global mach include have been taken over
to the individual drivers. Only a few of the definitions are really
used nowadays. Remove all the unneeded lines.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19995
Signed-off-by: Robert Marko <robimarko@gmail.com>
- shrink data structures
- avoid unnecessary divisions
- support GSO fraglist on tx
Reapply with fixed patch
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Use Linux kernel version 6.12 by default for loongarch64 target.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19980
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Boards such as [1] and [2] add an extra Ethernet port to Raspberry Pi (CM)5.
These typically use Realtek PCIe or USB Ethernet NICs. Include kmod-r8169 and
kmod-usb-net-rtl8152 by default to make it easy to configure LAN/WAN ports
with these parts on Raspberry Pi 5.
Because CM5 can fit in the same carrier boards as CM4, also ensure that both
devices have the same Ethernet NIC kmods.
[1]: https://www.waveshare.com/wiki/CM5-DUAL-ETH-MINI
[2]: https://www.waveshare.com/wiki/PCIe_TO_Gigabit_ETH_Board_(C)
Signed-off-by: Elbert Mai <code@elbertmai.com>
Link: https://github.com/openwrt/openwrt/pull/19384
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Certain boards have an at24(-compatible) EEPROM for storing various
parameters like MAC addresses. Enable support for this hardware across
the whole target.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
Backport fixes for Airoha pinctrl driver for PHY LED and MDIO bus. This
fix a copy-paste error for PHY LED and a misconfiguration for MT7530
embedded Switch MDIO bus GPIO pin to permit usage of external PHYs.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The RK356x/RK3588 SoCs support up to 10 serial ports.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19917
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Apart from improved power consumption, this fixes the runtime errors
from the pmdomain driver (failed to set idle on domain '%s')
Backport four clk fixes while at it.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19925
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
All devices supported by the Zynq target have either a Realtek or Marvell
PHY. The Vitesse PHY was enabled when the target was created (2d45ad07fc).
It's not used here, so it's safe to disable it.
Ethernet PHYs used by individual devices are listed below.
Device PHY
AVNET ZedBoard Marvell 88E1518
Digilent Zybo Realtek RTL8211E
Digilent Zybo Z7 Realtek RTL8211E or RTL8211F
Xilinx ZC702 Marvell 88E1116R
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19969
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This was done by executing these command:
$ make kernel_oldconfig CONFIG_TARGET=platform
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19969
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The devices are basically identical. The RAX3000Me can be with
ddr3 RAM.
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19760
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit adds ddr3 build for the ddr3 variant of the CMCC RAX3000Me
router.
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19760
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Hardware
--------
MediaTek MT7981 WiSoC
512MB DDR4 RAM
128MB SPI-NAND
MediaTek MT7981 2x2 DBDC 802.11ax 2T2R (2.4 / 5)
4 LAN MediaTek MT7531 PHY
1 WAN RTL8221B-VB-CG 2.5Gbps PHY
UART: 115200 8N1 3.3V
USB2 Port
PoE on WAN Port
MAC:
LAN MAC: label mac
WAN MAC: label mac + 1
2.4G MAC: label mac
5G MAC: label mac + 1 with LA bit set
Gotchas:
WAN LED does not light up (might require further DTS tweaks)
PoE on WAN port was not tested
This commit is heavily based on WR3000H one, I've just ported DTS differences
from the official image to get USB support and proper LED mapping.
Installation
------------
[Untested as I've received and used a transitional image from Cudy]
1. Connect to the serial port as described in the "Hardware" section.
2. Power on the device + press reset pin. Keep pressing reset pin to enter the U-Boot shell.
3. Download the OpenWrt initramfs image. Place it on an TFTP server
connected to the Cudy LAN ports. Make sure the server is reachable at
192.168.1.88. Rename the image to "cudy3000p.bin"
4. Download and boot the OpenWrt initramfs image.
$ tftpboot 0x46000000 cudy3000s.bin; bootm 0x46000000
5. Transfer the OpenWrt sysupgrade image to the device using scp.
Install with sysupgrade.
Signed-off-by: Michal Halva <hedik01@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19636
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa E52C is a compact network computer using the Rockchip RK3582
SoC.
- https://radxa.com/products/network-computer/e52c
Hardware
--------
- Dual Cortex-A76 and Quad Cortex-A55 CPU
- 5 TOPS NPU
- 2/4/8GB LPDDR4 RAM
- 16/32/64GB on-board eMMC
- microSD card slot
- 2x 2.5 Gigabit Ethernet ports
- USB 3.1 Gen1 Type-A HOST/OTG port
- USB Type-C debug port
- USB Type-C power port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa ROCK 5C (Lite) is a single board computer using the Rockchip
RK3588S2 (RK3582) SoC.
- https://radxa.com/products/rock5/5c
Hardware
--------
- Quad (Dual) Cortex-A76 and Quad Cortex-A55 CPU
- Mali-G610 MP4 GPU (5C only)
- 6 (5) TOPS NPU
- 1/2/4/8/16/32GB LPDDR4X RAM
- eMMC/SPI NOR flash connector
- microSD card slot
- Wi-Fi 6 (AIC8800D80, not yet supported)
- Gigabit Ethernet port with PoE (additional PoE HAT required)
- USB 3.1 Gen1 Type-A HOST/OTG port
- USB 3.1 Gen1 Type-A HOST port
- 2x USB 2.0 Type-A HOST ports
- FPC connector with PCIe 2.1 x1
- PWM fan connector
- 20x2 pin header
- USB Type-C power port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa ROCK 5 ITX(+) is a Mini-ITX form factor computer using the
Rockchip RK3588 SoC.
- https://radxa.com/products/rock5/5itx
- https://radxa.com/products/rock5/5itxp
Hardware
--------
- Quad Cortex-A76 and Quad Cortex-A55 CPU
- Mali-G610 MP4 GPU
- 6 TOPS NPU
- 4/8/16/24/32GB LPDDR5 RAM
- on-board eMMC
- 16MB SPI NOR flash
- microSD card slot
- 2x 2.5 Gigabit Ethernet ports with PoE (additional PoE module required)
- USB 3.1 Gen1 Type-C HOST/OTG port
- 4x USB 3.1 Gen1 Type-A HOST ports
- 2x USB 2.0 Type-A HOST ports
- M.2 M Key connector with PCIe 3.0 x2
- 4x SATA connectors (ITX only)
- 2nd M.2 M Key connector with PCIe 3.0 x2 (ITX+ only)
- M.2 E Key connector with PCIe 2.1 x1 and USB 2.0
- RTC battery socket for CR1220
- 4pin PWM fan connector
- Serial console pin header
- Front panel pin headers
- 24pin ATX power connector
- 5525 12V DC jack
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The Radxa ROCK 5B+ is a single board computer using the Rockchip
RK3588 SoC.
- https://radxa.com/products/rock5/5bp
Hardware
--------
- Quad Cortex-A76 and Quad Cortex-A55 CPU
- Mali-G610 MP4 GPU
- 6 TOPS NPU
- 4/8/16/24/32GB LPDDR5 RAM
- 16/32/64/128/256GB on-board eMMC (optional)
- 16MB SPI NOR flash
- microSD card slot
- Wi-Fi 6 (Realtek RTW8852BE)
- 2.5 Gigabit Ethernet port with PoE (additional PoE HAT required)
- USB 3.1 Gen1 Type-C HOST/OTG port
- 2x USB 3.1 Gen1 Type-A HOST ports
- 2x USB 2.0 Type-A HOST ports
- 2x M.2 M Key connectors with PCIe 3.0 x2
- M.2 B Key connector
- SIM card slot
- RTC battery connector
- PWM fan connector
- 20x2 pin header
- USB Type-C power port
Installation
------------
Uncompress the OpenWrt sysupgrade and write it to a micro SD card or
eMMC using dd.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa E52C.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5C and 5C Lite.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5 ITX and ITX+.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5B, 5B+, and 5T.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Radxa ROCK 5A.
Use power(green) LED instead of heartbeat(blue) LED.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport dts changes up to Linux v6.17 for Rockchip RK358x.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport gated-fixed-clk driver from Linux v6.13.
This is needed to fix a PCIe controller probe hang on the Radxa ROCK 5
ITX.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Link: https://github.com/openwrt/openwrt/pull/19867
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
So much code was distributed between phy/ethernet/dsa drivers. A lot
was already cleand up before. With this step the mdio bus gets its
own space and is no longer hidden inside the ethernet driver.
This commit is mostly a copy/paste that includes only minor changes.
- define prefixes are renamed to RTMDIO
- The driver is totally self contained (does not rely on SoC include)
- The DTS structure (mdio node below ethernet node) was kept
- The driver is added to the kernel config of all subtargets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19942
Signed-off-by: Robert Marko <robimarko@gmail.com>
The ethernet and mdio code will be splitted. The dsa driver depends
on proper loading of both, before switch setup can start. Sadly there
are severe cleanup issues in the probe() function if one of the
required devices is not available.
As a temporary workaround provide a dedicated check function that
verifies if the ethernet platform device driver is loaded and can
be used.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19942
Signed-off-by: Robert Marko <robimarko@gmail.com>
Use Unix LF style instead of Windows CRLF style.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19963
Signed-off-by: Robert Marko <robimarko@gmail.com>
At the end of RX NAPI polling the counter and mask registers are
cleaned up. Although this might run in parallel there is no
synchronization and the register modifications are some wild mix.
RTL83xx enables only the interrupt of a single ring while RTL93xx
just reactivates all interrupts (even for other NAPI threads).
Make use of the driver lock and only modify the interrupt bits that
the current thread owns.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19960
Signed-off-by: Robert Marko <robimarko@gmail.com>
Now that the counter registers work fine there is no need to
free buffers in software. Hardware will automatically block
input processing when software processing is too slow.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19960
Signed-off-by: Robert Marko <robimarko@gmail.com>
The receive path of the RTL93xx SoCs is currently discarding packets
in software. Analysis gives the following explanation:
- RX ring size registers are setup with the full software ring size
- When packets are received the packet counter registers are increased
- After RX processing the counter registers are changed the wrong way
- From then SOC is allowed to receive more packets than software allows
- Overflow interrupts are fired
- As a reaction to that the software drops packets
Change the processing as follows:
- Setup ring size registers with a headroom of 2 buffers
- Decrease the counter registers with the real work done
With this change no more overflow interrupts occur because the SoC
disables the queues before they can overflow or hit a buffer that is
still owned by the CPU.
Benchmark from single stream iperf3 run, with server process running
on ZyXEL XGS1210 (RTL930x).
iperf3 run before
-----------------------------------------------------------
Server listening on 5201 (test #1)
-----------------------------------------------------------
Accepted connection from 192.168.2.86, port 54412
[ 5] local 192.168.2.71 port 5201 connected to 192.168.2.86 port 54418
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 384 KBytes 3.14 Mbits/sec
[ 5] 1.00-2.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 2.00-3.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 3.00-4.01 sec 5.12 MBytes 42.8 Mbits/sec
[ 5] 4.01-5.00 sec 11.4 MBytes 95.8 Mbits/sec
[ 5] 5.00-6.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 6.00-7.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 7.00-8.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 8.00-9.00 sec 0.00 Bytes 0.00 bits/sec
[ 5] 9.00-10.00 sec 0.00 Bytes 0.00 bits/sec
iperf3 run after
-----------------------------------------------------------
Server listening on 5201 (test #1)
-----------------------------------------------------------
Accepted connection from 192.168.2.86, port 55228
[ 5] local 192.168.2.71 port 5201 connected to 192.168.2.86 port 55232
[ ID] Interval Transfer Bitrate
[ 5] 0.00-1.00 sec 22.8 MBytes 191 Mbits/sec
[ 5] 1.00-2.01 sec 25.4 MBytes 211 Mbits/sec
[ 5] 2.01-3.00 sec 25.4 MBytes 215 Mbits/sec
[ 5] 3.00-4.01 sec 26.5 MBytes 220 Mbits/sec
[ 5] 4.01-5.00 sec 26.2 MBytes 222 Mbits/sec
[ 5] 5.00-6.00 sec 26.9 MBytes 225 Mbits/sec
[ 5] 6.00-7.00 sec 27.0 MBytes 226 Mbits/sec
[ 5] 7.00-8.01 sec 26.9 MBytes 224 Mbits/sec
[ 5] 8.01-9.00 sec 26.5 MBytes 223 Mbits/sec
[ 5] 9.00-10.00 sec 26.8 MBytes 225 Mbits/sec
[ 5] 10.00-10.02 sec 640 KBytes 224 Mbits/sec
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19960
Signed-off-by: Robert Marko <robimarko@gmail.com>
Backport quirks for two SFP+ modules. Both support the RollBall protocol.
The fix for the FLYPRO module is queued in net-next tree.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Link: https://github.com/openwrt/openwrt/pull/19949
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
These patches hacked the set_eee() and get_eee() functions into
the phy_driver. Drop them with no consumer left.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19906
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Since we are using upstream PHY drivers there is no more need
for the downstream version. Side effect is that the SoC dependent
polling functions are no longer needed. This was always wrong
in this driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19906
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
A new version of the ZyXEL XGS1210-12 has been discovered in
the wild. It includes at least two known hardware changes
- lan9/lan10 use RTL8221B instead of RTL8226
- lan9/lan10 use different SMI busses
Pave the new device the way by splitting the existing DTS.
According to the vendor website the models are named
- A1 (first version): not explicetly labeled
- B1 (second version): Label Rev. B1 on device
Rename the current OpenWrt device definition to A1 as it was
made for the first version. To stay compatible with older
installations, add the old device name to the list of
supported devices.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19908
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The rt-loader currently only supports booting piggy backed lzma
compressed kernels. This requires a data layout where the kernel
directly follows the loader. That might not be sufficient for
more complex flash layouts.
Especially bootbase devices (like ZyXEL GS1920) will need some
kind of chain loading that needs to be explored yet.
Enhance the rt-loader as follows:
- Allow to build as standalone version
- In this case a flash start address is given
- During boot loader will search the ROM starting from that address
- If it finds a uImage this will be loaded into RAM
- Afterwards it will be decompressed to its load address
- While we are here add uncompressed uImage support
As always the implementation tries to be as simple as possible.
- uImage detection works without magics
- uImage will be loaded to highest possible memory address
- Documentation in Makefile has been adapted accordingly
Funny side fact: A standalone rt-loader can chain load a piggy
backed rt-loader from flash.
During bootup loader will show
rt-loader
Running on RTL8380M (chip id 6275C) with 256MB
Relocate 15760 bytes from 0x82000000 to 0x8ffa0000
Searching for uImage starting at 0xb45a0000 ...
uImage 'MIPS OpenWrt Linux-6.12.40' found at 0xb45a0000 with load address 0x80100000
Copy 2923034 bytes of image data to 0x8fcd61e6 ...
Extract image with 2923034 bytes from 0x8fcd61e6 to 0x80100000 ...
Final kernel size is 2923034 bytes
Booting kernel from 0x80100000 ...
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19832
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Provide a crc32 function (will be needed later). Do some
minor naming and coding cleanups
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19832
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Registers must not be accessed in parallel by multiple drivers.
Read-modify-write operations are not atomic, and the result of parallel
access is undefined.
The MAC_L2_GLOBAL_CTRL2 register is essentially a pin configuration
register and is represented by a pinmux node in the devicetree. Operations
on this register by the realtek,rtl838x-eth driver must therefore also be
reflected in the devicetree.
Since the MDIO sets used are board-specific, the pins must be enabled in
the board’s devicetree. This can be achieved using the pinctrl properties
for the realtek,rtl83xx-switch.
&switch0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
<&pinmux_enable_mdc_mdio_1>;
....
};
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
The pinmux-related registers on the RTL931X SoC family are spread across
various non-consecutive registers. It might be tempting to modify them
directly in a specific driver (SPI, LED, etc.), but this would cause issues
with parallel, non-locked read-modify-write operations, which are required
to update individual portions of these registers.
Instead, it is better to use the devicetree pinctrl properties to define
the correct configurations for the various operation modes.
One important setting here is the LED Sync bit. This allows the LED
controller to generate an additional positive edge on the `STCP`
("STore Clock Pin", also known as `RCLK`) of the LED shift register after
the actual content has already been shifted in using the normal shift
clock. The LED shift register is then expected to copy the content from the
shift register section into the storage registers, which act as the actual
LED output control. This functionality is available in, and commonly used
with, the SNx4HC595 family of shift registers.
To activate it, simply register it in the default state of the
"realtek,rtl83xx-switch" node:
&switch0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_led_sync>;
....
};
It would be nicer when this can be directly added to the led subnode. But
for this to work, `realtek,rtl9300-leds` must first be an actual driver
(known to the driver core).
[1] https://www.ti.com/lit/ds/symlink/sn74hc595.pdf
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
The MAC_L2_GLOBAL_CTRL2 register is primarily used for pin configuration.
It is necessary to select specific modes for pins or to free them for use
as GPIOs.
Fixes: 9dbc04785c ("realtek: add rtl8231-aux to rtl931x.dtsi")
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
The pinmux-related registers on the RTL930X SoC family are spread across
various non-consecutive registers. It might be tempting to modify them
directly in a specific driver (SPI, LED, etc.), but this would cause issues
with parallel, non-locked read-modify-write operations, which are required
to update individual portions of these registers.
Instead, it is better to use the devicetree pinctrl properties to define
the correct configurations for the various operation modes.
One important setting here is the LED Sync bit. This allows the LED
controller to generate an additional positive edge on the `STCP`
("STore Clock Pin", also known as `RCLK`) of the LED shift register after
the actual content has already been shifted in using the normal shift
clock. The LED shift register is then expected to copy the content from the
shift register section into the storage registers, which act as the actual
LED output control. This functionality is available in, and commonly used
with, the SNx4HC595 family of shift registers.
To activate it, simply register it in the default state of the
"realtek,rtl83xx-switch" node:
&switch0 {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_led_sync>;
....
};
It would be nicer when this can be directly added to the led subnode. But
for this to work, `realtek,rtl9300-leds` must first be an actual driver
(known to the driver core).
[1] https://www.ti.com/lit/ds/symlink/sn74hc595.pdf
Suggested-by: Bevan Weiss <bevan.weiss@gmail.com>
Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/19815
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add the NPU and reserved memory node for AN7581 dtsi since it's not
supported.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Major backport of upstream patch for support of multiple feature of the
Airoha Ethernet driver.
Feature backported are TSO, Jumbo packet, Offload and initial Wlan
Offload support.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport trivial fixes from upstream related to pinctrl and ethernet
driver.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport patch adding support for AN7581 Ethernet PHY based on the same
Mediatek embedded Switch PHY.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Mediatek PHY patch has been merged upstream. Reintroduce them to
backport directory as the same PHY is also needed for Airoha target.
All the affected patch automatically refreshed.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport support for Aeonsemi AS121xxx PHY. The PHY require dedicated
firmware to be loaded to correctly work and support a big family of
Aeonsemi PHY that provide from 1G to 10G speed.
Automatically refresh all affected patch and file (rtl PHY).
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Replace thermal patch with upstream version. The thermal maintainer
reported that the sysfs entry are considered deprecated and that slope
and offset should be handled internally to the driver.
Link: https://github.com/openwrt/openwrt/pull/19816
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Fix the model name in DTS compatible, Makefiles and board scripts by
using dash instead of comma or underscore. This aligns it with other
examples in OpenWrt and makes in consistent in all places where the
board model is used.
'tplink,tl-st1008f,v2' --> 'tplink,tl-st1008f-v2'
'tplink,tl-st1008f_v2' --> 'tplink,tl-st1008f-v2'
Fixes: 39b9b491bb ("realtek: add support for TP-Link TL-ST1008F v2.0")
Fixes: #19930
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19934
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Backport a patch from upstream kernel 6.17-rc4 which fixes a regression
introduced in the latest stable kernel versions.
This is already in the Linus stable queues for the next minor kernel
updates.
Fixes: 1c92e468d5 ("kernel: bump 6.6 to 6.6.103")
Fixes: f39c7e103f ("kernel: bump 6.12 to 6.12.43")
Reported-by: Goetz Goerisch <ggoerisch@gmail.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Currently the calculation for the CMU (even) SerDes works similar
to this pseudo code.
analog_backend_serdes = get_analog_serdes(frontend_serdes);
even_backend_serdes = analog_backend_serdes & ~1;
write_to(even_backend_serdes);
Because of the SerDes layout and frontend/backend mapping this can
be swapped to the following order with the same resulting Serdes.
even_frontend_serdes = frontend_serdes ~1;
analog_backend_serdes = get_analog_serdes(even_frontend_serdes);
write_to(analog_backed_serdes);
In the later example the frontend/backend mapping code is already
in our new functions. So swap the calculation logic and use the
new access functions. This allows to finally drop the old access
functions without mapping.
From now on all RTL931x SerDes functions will use a consistent
frontend view.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL931x has 14 frontend and at least 26 backend serdes. Currently
the programming functions always need to determine the right backend
serdes from the given frontend serdes on their own. We plan to provide
a consistent serdes mapping to all callers.
As the third step make use of these new functions whenever we want to
access the "digital 2" pages. The pages are mapped starting at 0x200.
So the function conversion is as simple as this:
Old:
dsds = (sds - 1) * 2;
rtmdio_931x_read_sds_phy(dsds + 1, page, ...)
New:
rtmdio_931x_read_sds_phy_new(sds, page + 0x200, ...)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The more we step down into the SerDes deeps the more confusing it
gets. Nevertheless it is not to late to fix a wrong assumption.
Until now it seemed as if the frontend/backend SerDes mapping is
totally without intersection. This is not true.
The backend SerDes mapping is also dependent on the mode. Especially
the proprietary Realtek XSGMII mode stands out from all other
mappings. So fix the descriptions and the calculation of the third
page package (digital 2 aka XSGMII 2).
As it was not yet used it had no impact.
Fixes: a4cbb44c1b ("realtek: convert access to RTL931x analog serdes pages")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The RTL931x has 14 frontend and at least 26 backend serdes. Currently
the programming functions always need to determine the right backend
serdes from the given frontend serdes on their own. We plan to provide
a consistent serdes mapping to all callers.
As the second step make use of these new functions whenever we
want to access the digital 1 pages. The pages are mapped starting
at 0x100. So the function conversion is as simple as this:
Old:
dsds = (sds - 1) * 2;
rtmdio_931x_read_sds_phy(dsds, page, ...)
New:
rtmdio_931x_read_sds_phy_new(sds, page + 0x100, ...)
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19873
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
For some reason 3 of the 4 mdio access functions contain an
artifical delay of 10ms. While it might have been part of
older Realtek SDKs it can no longer be found in current ones.
Remove the delays.
While we are here remove the pre-access bus ready checks.
It is sufficient to run them after the command start. If
anything fails the caller will get an error. This is the
same behaviour as for the other targets.
Finally cleanup the error handling. Something like this makes
no sense at all.
err = rtmdio_838x_smi_wait_op(100000);
if (err)
goto errout;
err = 0;
errout:
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19901
Signed-off-by: Robert Marko <robimarko@gmail.com>
When sending llc packets with vlan tx offload, the hardware fails to
actually add the tag. Deal with this by fixing it up in software.
Fixes: https://github.com/openwrt/openwrt/issues/19916
Reported-by: Thibaut VARENE <hacks@slashdirt.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Most drivers have this as const. Especially upstream in the kernel.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19911
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Import upstream patches fixing issues with unreliable temperature
reading on some batches of the MediaTek MT7988 SoCs.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
