43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
93 lines
2.4 KiB
Plaintext
93 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#define STRINGIZE(s) #s
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#define LAN_LABEL(p, s) STRINGIZE(p ## s)
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#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
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#define PHY_C22(p, n) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c22"; \
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};
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#define PHY_C22_SFP(p, n, s) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c22"; \
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sfp = <&sfp##s>; \
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};
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#define PHY_C45(p, n) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c45"; \
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};
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#define PHY_C45_PAIR_ORDER(p, n, po) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c45"; \
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enet-phy-pair-order = <##po>; \
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};
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#define SWITCH_PORT(p, l, m) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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phy-handle = <&phy##p>; \
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phy-mode = #m ; \
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};
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#define SWITCH_PORT_SDS(p, l, s, i, m) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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pcs-handle = <&serdes##s i>; \
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phy-handle = <&phy##p>; \
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phy-mode = #m ; \
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};
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#define SWITCH_PORT_LED(p, l, s, i, c, m) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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led-set = <##c>; \
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pcs-handle = <&serdes##s i>; \
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phy-handle = <&phy##p>; \
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phy-mode = #m ; \
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};
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#define SWITCH_PORT_SFP(p, l, s, c, g) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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led-set = <##c>; \
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pcs-handle = <&serdes##s 0>; \
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phy-mode = "1000base-x"; \
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sfp = <&sfp##g>; \
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managed = "in-band-status"; \
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};
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/* LED Set mode definitions */
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#define RTL93XX_LED_SET_NONE (0)
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#define RTL93XX_LED_SET_10G (1 << 0)
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#define RTL93XX_LED_SET_5G (1 << 1)
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#define RTL93XX_LED_SET_2P5G (1 << 3)
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#define RTL93XX_LED_SET_1G (1 << 5)
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#define RTL93XX_LED_SET_100M (1 << 7)
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#define RTL93XX_LED_SET_10M (1 << 8)
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#define RTL93XX_LED_SET_LINK (1 << 9)
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#define RTL93XX_LED_SET_LINK_BLINK (1 << 10)
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#define RTL93XX_LED_SET_ACT (1 << 11)
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#define RTL93XX_LED_SET_RX (1 << 12)
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#define RTL93XX_LED_SET_TX (1 << 13)
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#define RTL93XX_LED_SET_COLLISION (1 << 14)
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#define RTL93XX_LED_SET_DUPLEX (1 << 15)
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/* LED Interface modes */
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#define RTL93XX_LED_MODE_SERIAL 1
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#define RTL93XX_LED_MODE_SINGLE_COLOR_SCAN 2
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#define RTL93XX_LED_MODE_BI_COLOR_SCAN 3
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