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realtek: dts: add link index cell to pcs-handle phandles

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A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.

The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.

Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.

No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.

Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
This commit is contained in:
Jonas Jelonek 2026-05-25 13:09:28 +00:00
parent b3faefcc32
commit 43562f97e7
No known key found for this signature in database
66 changed files with 933 additions and 928 deletions
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10
target/linux/realtek/dts/macros.dtsi
View File

@ -40,21 +40,21 @@
phy-mode = #m ; \
};
#define SWITCH_PORT_SDS(p, l, s, m) \
#define SWITCH_PORT_SDS(p, l, s, i, m) \
port##p: port@##p { \
reg = <##p>; \
label = SWITCH_PORT_LABEL(l) ; \
pcs-handle = <&serdes##s>; \
pcs-handle = <&serdes##s i>; \
phy-handle = <&phy##p>; \
phy-mode = #m ; \
};
#define SWITCH_PORT_LED(p, l, s, c, m) \
#define SWITCH_PORT_LED(p, l, s, i, c, m) \
port##p: port@##p { \
reg = <##p>; \
label = SWITCH_PORT_LABEL(l) ; \
led-set = <##c>; \
pcs-handle = <&serdes##s>; \
pcs-handle = <&serdes##s i>; \
phy-handle = <&phy##p>; \
phy-mode = #m ; \
};
@ -64,7 +64,7 @@
reg = <##p>; \
label = SWITCH_PORT_LABEL(l) ; \
led-set = <##c>; \
pcs-handle = <&serdes##s>; \
pcs-handle = <&serdes##s 0>; \
phy-mode = "1000base-x"; \
sfp = <&sfp##g>; \
managed = "in-band-status"; \

4
target/linux/realtek/dts/rtl8380_d-link_dgs-1210-10mp-f.dts
View File

@ -103,7 +103,7 @@
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -112,7 +112,7 @@
port@26 {
reg = <26>;
label = "lan10";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

4
target/linux/realtek/dts/rtl8380_engenius_ews2910p.dtsi
View File

@ -199,7 +199,7 @@
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -208,7 +208,7 @@
port@26 {
reg = <26>;
label = "lan10";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

4
target/linux/realtek/dts/rtl8380_hpe_1920-8g.dtsi
View File

@ -85,7 +85,7 @@
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -97,7 +97,7 @@
port@26 {
reg = <26>;
label = "lan10";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

4
target/linux/realtek/dts/rtl8380_linksys_lgs310c.dts
View File

@ -191,7 +191,7 @@
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -200,7 +200,7 @@
port@26 {
reg = <26>;
label = "lan10";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

4
target/linux/realtek/dts/rtl8380_netgear_gs110tpp-v1.dts
View File

@ -61,7 +61,7 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
};
};

4
target/linux/realtek/dts/rtl8380_netgear_gs110tup-v1.dts
View File

@ -51,12 +51,12 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
port@24 {
reg = <24>;
label = "lan10";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
/* i2c and gpios not yet identified */

4
target/linux/realtek/dts/rtl8380_netgear_gs310tp-v1.dts
View File

@ -56,7 +56,7 @@
port24: port@24 {
reg = <24>;
label = SWITCH_PORT_LABEL(9);
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
@ -66,7 +66,7 @@
port26: port@26 {
reg = <26>;
label = SWITCH_PORT_LABEL(10);
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;

2
target/linux/realtek/dts/rtl8380_panasonic_m8eg-pn28080k.dts
View File

@ -102,7 +102,7 @@
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;

4
target/linux/realtek/dts/rtl8380_tplink_sg2210p-v3.dts
View File

@ -12,7 +12,7 @@
port24: port@24 {
reg = <24>;
label = "lan-sfp2";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
@ -23,7 +23,7 @@
port26: port@26 {
reg = <26>;
label = "lan-sfp1";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;

4
target/linux/realtek/dts/rtl8380_tplink_sg2xxx.dtsi
View File

@ -168,7 +168,7 @@
port24: port@24 {
reg = <24>;
label = SWITCH_PORT_LABEL(9);
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
@ -178,7 +178,7 @@
port26: port@26 {
reg = <26>;
label = SWITCH_PORT_LABEL(10);
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;

4
target/linux/realtek/dts/rtl8380_zyxel_gs1900-10hp-a1.dts
View File

@ -57,7 +57,7 @@
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -66,7 +66,7 @@
port@26 {
reg = <26>;
label = "lan10";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

24
target/linux/realtek/dts/rtl8382_apresia_aplgs120gtss.dts
View File

@ -229,14 +229,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -247,10 +247,10 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, qsgmii)
SWITCH_PORT_SDS(24, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

4
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-10p.dts
View File

@ -102,7 +102,7 @@
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -111,7 +111,7 @@
port@26 {
reg = <26>;
label = "lan10";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

24
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-16.dts
View File

@ -40,14 +40,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -58,10 +58,10 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, qsgmii)
SWITCH_PORT_SDS(24, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

24
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-20.dts
View File

@ -40,14 +40,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -58,10 +58,10 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, qsgmii)
SWITCH_PORT_SDS(24, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

36
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-26.dts
View File

@ -79,14 +79,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -97,19 +97,19 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
port@24 {
reg = <24>;
label = "lan25";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -118,7 +118,7 @@
port@26 {
reg = <26>;
label = "lan26";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

40
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-28_common.dtsi
View File

@ -40,14 +40,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -58,19 +58,19 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 4, qsgmii)
SWITCH_PORT_SDS(25, 26, 4, qsgmii)
SWITCH_PORT_SDS(26, 27, 4, qsgmii)
SWITCH_PORT_SDS(27, 28, 4, qsgmii)
SWITCH_PORT_SDS(24, 25, 4, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 4, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 4, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 4, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

24
target/linux/realtek/dts/rtl8382_hpe_1920-16g.dts
View File

@ -21,19 +21,19 @@
SWITCH_PORT(14, 7, internal)
SWITCH_PORT(15, 8, internal)
SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, qsgmii)
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, qsgmii)
SWITCH_PORT_SDS(24, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(25, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(26, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(27, 20, 4, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

40
target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi
View File

@ -23,14 +23,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -41,19 +41,19 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 4, qsgmii)
SWITCH_PORT_SDS(25, 26, 4, qsgmii)
SWITCH_PORT_SDS(26, 27, 4, qsgmii)
SWITCH_PORT_SDS(27, 28, 4, qsgmii)
SWITCH_PORT_SDS(24, 25, 4, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 4, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 4, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 4, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

16
target/linux/realtek/dts/rtl8382_inaba_aml2-17gp.dts
View File

@ -121,14 +121,14 @@
SWITCH_PORT(14, 7, internal)
SWITCH_PORT(15, 8, internal)
SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, qsgmii)
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
port@24 {
reg = <24>;

32
target/linux/realtek/dts/rtl8382_iodata_bsh-g24mb.dts
View File

@ -155,14 +155,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -173,14 +173,14 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

16
target/linux/realtek/dts/rtl8382_panasonic_m16eg-pn28160k.dts
View File

@ -140,14 +140,14 @@
SWITCH_PORT(14, 7, internal)
SWITCH_PORT(15, 8, internal)
SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, qsgmii)
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

32
target/linux/realtek/dts/rtl8382_panasonic_m24eg-pn28240k.dts
View File

@ -141,14 +141,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -159,14 +159,14 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

32
target/linux/realtek/dts/rtl8382_tplink_t1600g-28ts-v3.dts
View File

@ -128,14 +128,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -146,14 +146,14 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
port@28 {
ethernet = <&ethernet0>;

16
target/linux/realtek/dts/rtl8382_zyxel_gs1900-16-a1.dts
View File

@ -21,14 +21,14 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, qsgmii)
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
};
};

36
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24.dtsi
View File

@ -70,14 +70,14 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -88,19 +88,19 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
port@24 {
reg = <24>;
label = "lan25";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -109,7 +109,7 @@
port@26 {
reg = <26>;
label = "lan26";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

32
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24e-a1.dts
View File

@ -40,14 +40,14 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(1, 1, 0, qsgmii)
SWITCH_PORT_SDS(0, 2, 0, qsgmii)
SWITCH_PORT_SDS(3, 3, 0, qsgmii)
SWITCH_PORT_SDS(2, 4, 0, qsgmii)
SWITCH_PORT_SDS(5, 5, 1, qsgmii)
SWITCH_PORT_SDS(4, 6, 1, qsgmii)
SWITCH_PORT_SDS(7, 7, 1, qsgmii)
SWITCH_PORT_SDS(6, 8, 1, qsgmii)
SWITCH_PORT_SDS(1, 1, 0, 1, qsgmii)
SWITCH_PORT_SDS(0, 2, 0, 0, qsgmii)
SWITCH_PORT_SDS(3, 3, 0, 3, qsgmii)
SWITCH_PORT_SDS(2, 4, 0, 2, qsgmii)
SWITCH_PORT_SDS(5, 5, 1, 1, qsgmii)
SWITCH_PORT_SDS(4, 6, 1, 0, qsgmii)
SWITCH_PORT_SDS(7, 7, 1, 3, qsgmii)
SWITCH_PORT_SDS(6, 8, 1, 2, qsgmii)
SWITCH_PORT(9, 9, internal)
SWITCH_PORT(8, 10, internal)
@ -58,14 +58,14 @@
SWITCH_PORT(15, 15, internal)
SWITCH_PORT(14, 16, internal)
SWITCH_PORT_SDS(17, 17, 2, qsgmii)
SWITCH_PORT_SDS(16, 18, 2, qsgmii)
SWITCH_PORT_SDS(19, 19, 2, qsgmii)
SWITCH_PORT_SDS(18, 20, 2, qsgmii)
SWITCH_PORT_SDS(21, 21, 3, qsgmii)
SWITCH_PORT_SDS(20, 22, 3, qsgmii)
SWITCH_PORT_SDS(23, 23, 3, qsgmii)
SWITCH_PORT_SDS(22, 24, 3, qsgmii)
SWITCH_PORT_SDS(17, 17, 2, 1, qsgmii)
SWITCH_PORT_SDS(16, 18, 2, 0, qsgmii)
SWITCH_PORT_SDS(19, 19, 2, 3, qsgmii)
SWITCH_PORT_SDS(18, 20, 2, 2, qsgmii)
SWITCH_PORT_SDS(21, 21, 3, 1, qsgmii)
SWITCH_PORT_SDS(20, 22, 3, 0, qsgmii)
SWITCH_PORT_SDS(23, 23, 3, 3, qsgmii)
SWITCH_PORT_SDS(22, 24, 3, 2, qsgmii)
};
};

32
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24ep-a1.dts
View File

@ -34,14 +34,14 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -52,13 +52,13 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
};
};

36
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-a1.dts
View File

@ -76,14 +76,14 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -94,19 +94,19 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
port@24 {
reg = <24>;
label = "lan25";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -115,7 +115,7 @@
port@26 {
reg = <26>;
label = "lan26";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

36
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-b1.dts
View File

@ -72,14 +72,14 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
@ -90,20 +90,20 @@
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
port@24 {
reg = <24>;
label = "lan25";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -112,7 +112,7 @@
port@26 {
reg = <26>;
label = "lan26";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

12
target/linux/realtek/dts/rtl838x.dtsi
View File

@ -252,27 +252,27 @@
serdes0: serdes@0 {
reg = <0>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes1: serdes@1 {
reg = <1>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes2: serdes@2 {
reg = <2>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes3: serdes@3 {
reg = <3>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes4: serdes@4 {
reg = <4>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes5: serdes@5 {
reg = <5>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
};

8
target/linux/realtek/dts/rtl8391_zyxel_gs1920-24hp-v2.dts
View File

@ -126,9 +126,9 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
};
};

8
target/linux/realtek/dts/rtl8392_zyxel_gs1920-24hp-v1.dts
View File

@ -80,9 +80,9 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(48, 25, 12, qsgmii)
SWITCH_PORT_SDS(49, 26, 12, qsgmii)
SWITCH_PORT_SDS(50, 27, 12, qsgmii)
SWITCH_PORT_SDS(51, 28, 12, qsgmii)
SWITCH_PORT_SDS(48, 25, 12, 0, qsgmii)
SWITCH_PORT_SDS(49, 26, 12, 1, qsgmii)
SWITCH_PORT_SDS(50, 27, 12, 2, qsgmii)
SWITCH_PORT_SDS(51, 28, 12, 3, qsgmii)
};
};

104
target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts
View File

@ -85,64 +85,64 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
SWITCH_PORT_SDS(48, 49, 12, qsgmii)
SWITCH_PORT_SDS(49, 50, 12, qsgmii)
SWITCH_PORT_SDS(50, 51, 12, qsgmii)
SWITCH_PORT_SDS(51, 52, 12, qsgmii)
SWITCH_PORT_SDS(48, 49, 12, 0, qsgmii)
SWITCH_PORT_SDS(49, 50, 12, 1, qsgmii)
SWITCH_PORT_SDS(50, 51, 12, 2, qsgmii)
SWITCH_PORT_SDS(51, 52, 12, 3, qsgmii)
/* CPU-Port */
port@52 {

24
target/linux/realtek/dts/rtl8393_edgecore_ecs4100-12ph.dts
View File

@ -250,19 +250,19 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(48, 9, 12, qsgmii)
SWITCH_PORT_SDS(49, 10, 12, qsgmii)
SWITCH_PORT_SDS(50, 11, 12, qsgmii)
SWITCH_PORT_SDS(51, 12, 12, qsgmii)
SWITCH_PORT_SDS(48, 9, 12, 0, qsgmii)
SWITCH_PORT_SDS(49, 10, 12, 1, qsgmii)
SWITCH_PORT_SDS(50, 11, 12, 2, qsgmii)
SWITCH_PORT_SDS(51, 12, 12, 3, qsgmii)
port@52 {
ethernet = <&ethernet0>;

8
target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
View File

@ -99,10 +99,10 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(48, 49, 12, qsgmii)
SWITCH_PORT_SDS(49, 50, 12, qsgmii)
SWITCH_PORT_SDS(50, 51, 12, qsgmii)
SWITCH_PORT_SDS(51, 52, 12, qsgmii)
SWITCH_PORT_SDS(48, 49, 12, 0, qsgmii)
SWITCH_PORT_SDS(49, 50, 12, 1, qsgmii)
SWITCH_PORT_SDS(50, 51, 12, 2, qsgmii)
SWITCH_PORT_SDS(51, 52, 12, 3, qsgmii)
};
};

8
target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
View File

@ -90,10 +90,10 @@
&switch0 {
ethernet-ports {
SWITCH_PORT_SDS(48, 50, 12, qsgmii)
SWITCH_PORT_SDS(49, 52, 12, qsgmii)
SWITCH_PORT_SDS(50, 49, 12, qsgmii)
SWITCH_PORT_SDS(51, 51, 12, qsgmii)
SWITCH_PORT_SDS(48, 50, 12, 0, qsgmii)
SWITCH_PORT_SDS(49, 52, 12, 1, qsgmii)
SWITCH_PORT_SDS(50, 49, 12, 2, qsgmii)
SWITCH_PORT_SDS(51, 51, 12, 3, qsgmii)
};
};

96
target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
View File

@ -87,59 +87,59 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
port@52 {
ethernet = <&ethernet0>;

100
target/linux/realtek/dts/rtl8393_netgear_gs750e.dts
View File

@ -174,64 +174,64 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
port@48 {
reg = <48>;
label = "lan49";
pcs-handle = <&serdes12>;
pcs-handle = <&serdes12 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
/* i2c and gpio not yet identified */
@ -239,7 +239,7 @@
port@49 {
reg = <49>;
label = "lan50";
pcs-handle = <&serdes13>;
pcs-handle = <&serdes13 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
/* i2c and gpio not yet identified */

96
target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
View File

@ -306,59 +306,59 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
port@52 {
ethernet = <&ethernet0>;

96
target/linux/realtek/dts/rtl8393_tplink_sg2452p-v4.dts
View File

@ -348,59 +348,59 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
/* CPU-Port */
port@52 {

100
target/linux/realtek/dts/rtl8393_zyxel_gs1900-48.dtsi
View File

@ -313,65 +313,65 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
/* SFP cages */
port@48 {
reg = <48>;
label = "lan49";
pcs-handle = <&serdes12>;
pcs-handle = <&serdes12 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp0>;
@ -380,7 +380,7 @@
port@49 {
reg = <49>;
label = "lan50";
pcs-handle = <&serdes13>;
pcs-handle = <&serdes13 0>;
phy-mode = "1000base-x";
managed = "in-band-status";
sfp = <&sfp1>;

28
target/linux/realtek/dts/rtl839x.dtsi
View File

@ -265,59 +265,59 @@
serdes0: serdes@0 {
reg = <0>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes1: serdes@1 {
reg = <1>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes2: serdes@2 {
reg = <2>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes3: serdes@3 {
reg = <3>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes4: serdes@4 {
reg = <4>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes5: serdes@5 {
reg = <5>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes6: serdes@6 {
reg = <6>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes7: serdes@7 {
reg = <7>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes8: serdes@8 {
reg = <8>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes9: serdes@9 {
reg = <9>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes10: serdes@10 {
reg = <10>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes11: serdes@11 {
reg = <11>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes12: serdes@12 {
reg = <12>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes13: serdes@13 {
reg = <13>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
};

48
target/linux/realtek/dts/rtl839x_zyxel_gs1920-24hp-common.dtsi
View File

@ -188,32 +188,32 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
/* CPU-Port */
port@52 {

48
target/linux/realtek/dts/rtl9301_d-link_dgs-1250-28x.dts
View File

@ -261,32 +261,32 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 1, 0, 0, qsgmii)
SWITCH_PORT_LED(1, 2, 0, 0, qsgmii)
SWITCH_PORT_LED(2, 3, 0, 0, qsgmii)
SWITCH_PORT_LED(3, 4, 0, 0, qsgmii)
SWITCH_PORT_LED(4, 5, 1, 0, qsgmii)
SWITCH_PORT_LED(5, 6, 1, 0, qsgmii)
SWITCH_PORT_LED(6, 7, 1, 0, qsgmii)
SWITCH_PORT_LED(7, 8, 1, 0, qsgmii)
SWITCH_PORT_LED(0, 1, 0, 0, 0, qsgmii)
SWITCH_PORT_LED(1, 2, 0, 1, 0, qsgmii)
SWITCH_PORT_LED(2, 3, 0, 2, 0, qsgmii)
SWITCH_PORT_LED(3, 4, 0, 3, 0, qsgmii)
SWITCH_PORT_LED(4, 5, 1, 0, 0, qsgmii)
SWITCH_PORT_LED(5, 6, 1, 1, 0, qsgmii)
SWITCH_PORT_LED(6, 7, 1, 2, 0, qsgmii)
SWITCH_PORT_LED(7, 8, 1, 3, 0, qsgmii)
SWITCH_PORT_LED(8, 9, 2, 0, usxgmii)
SWITCH_PORT_LED(9, 10, 2, 0, usxgmii)
SWITCH_PORT_LED(10, 11, 2, 0, usxgmii)
SWITCH_PORT_LED(11, 12, 2, 0, usxgmii)
SWITCH_PORT_LED(12, 13, 2, 0, usxgmii)
SWITCH_PORT_LED(13, 14, 2, 0, usxgmii)
SWITCH_PORT_LED(14, 15, 2, 0, usxgmii)
SWITCH_PORT_LED(15, 16, 2, 0, usxgmii)
SWITCH_PORT_LED(8, 9, 2, 0, 0, usxgmii)
SWITCH_PORT_LED(9, 10, 2, 1, 0, usxgmii)
SWITCH_PORT_LED(10, 11, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(11, 12, 2, 3, 0, usxgmii)
SWITCH_PORT_LED(12, 13, 2, 4, 0, usxgmii)
SWITCH_PORT_LED(13, 14, 2, 5, 0, usxgmii)
SWITCH_PORT_LED(14, 15, 2, 6, 0, usxgmii)
SWITCH_PORT_LED(15, 16, 2, 7, 0, usxgmii)
SWITCH_PORT_LED(16, 17, 3, 0, usxgmii)
SWITCH_PORT_LED(17, 18, 3, 0, usxgmii)
SWITCH_PORT_LED(18, 19, 3, 0, usxgmii)
SWITCH_PORT_LED(19, 20, 3, 0, usxgmii)
SWITCH_PORT_LED(20, 21, 3, 0, usxgmii)
SWITCH_PORT_LED(21, 22, 3, 0, usxgmii)
SWITCH_PORT_LED(22, 23, 3, 0, usxgmii)
SWITCH_PORT_LED(23, 24, 3, 0, usxgmii)
SWITCH_PORT_LED(16, 17, 3, 0, 0, usxgmii)
SWITCH_PORT_LED(17, 18, 3, 1, 0, usxgmii)
SWITCH_PORT_LED(18, 19, 3, 2, 0, usxgmii)
SWITCH_PORT_LED(19, 20, 3, 3, 0, usxgmii)
SWITCH_PORT_LED(20, 21, 3, 4, 0, usxgmii)
SWITCH_PORT_LED(21, 22, 3, 5, 0, usxgmii)
SWITCH_PORT_LED(22, 23, 3, 6, 0, usxgmii)
SWITCH_PORT_LED(23, 24, 3, 7, 0, usxgmii)
SWITCH_PORT_SFP(24, 25, 4, 1, 0)
SWITCH_PORT_SFP(25, 26, 6, 1, 1)

48
target/linux/realtek/dts/rtl9301_linksys_lgs328x_nand_common.dtsi
View File

@ -84,32 +84,32 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, usxgmii)
SWITCH_PORT_SDS(9, 10, 2, usxgmii)
SWITCH_PORT_SDS(10, 11, 2, usxgmii)
SWITCH_PORT_SDS(11, 12, 2, usxgmii)
SWITCH_PORT_SDS(12, 13, 2, usxgmii)
SWITCH_PORT_SDS(13, 14, 2, usxgmii)
SWITCH_PORT_SDS(14, 15, 2, usxgmii)
SWITCH_PORT_SDS(15, 16, 2, usxgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, usxgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, usxgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, usxgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, usxgmii)
SWITCH_PORT_SDS(12, 13, 2, 4, usxgmii)
SWITCH_PORT_SDS(13, 14, 2, 5, usxgmii)
SWITCH_PORT_SDS(14, 15, 2, 6, usxgmii)
SWITCH_PORT_SDS(15, 16, 2, 7, usxgmii)
SWITCH_PORT_SDS(16, 17, 3, usxgmii)
SWITCH_PORT_SDS(17, 18, 3, usxgmii)
SWITCH_PORT_SDS(18, 19, 3, usxgmii)
SWITCH_PORT_SDS(19, 20, 3, usxgmii)
SWITCH_PORT_SDS(20, 21, 3, usxgmii)
SWITCH_PORT_SDS(21, 22, 3, usxgmii)
SWITCH_PORT_SDS(22, 23, 3, usxgmii)
SWITCH_PORT_SDS(23, 24, 3, usxgmii)
SWITCH_PORT_SDS(16, 17, 3, 0, usxgmii)
SWITCH_PORT_SDS(17, 18, 3, 1, usxgmii)
SWITCH_PORT_SDS(18, 19, 3, 2, usxgmii)
SWITCH_PORT_SDS(19, 20, 3, 3, usxgmii)
SWITCH_PORT_SDS(20, 21, 3, 4, usxgmii)
SWITCH_PORT_SDS(21, 22, 3, 5, usxgmii)
SWITCH_PORT_SDS(22, 23, 3, 6, usxgmii)
SWITCH_PORT_SDS(23, 24, 3, 7, usxgmii)
SWITCH_PORT_SFP(24, 25, 4, 0, 0)
SWITCH_PORT_SFP(25, 26, 6, 0, 1)

48
target/linux/realtek/dts/rtl9301_zyxel_xgs1930-28hp.dts
View File

@ -377,32 +377,32 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 1, 0, 0, qsgmii)
SWITCH_PORT_LED(1, 2, 0, 0, qsgmii)
SWITCH_PORT_LED(2, 3, 0, 0, qsgmii)
SWITCH_PORT_LED(3, 4, 0, 0, qsgmii)
SWITCH_PORT_LED(4, 5, 1, 0, qsgmii)
SWITCH_PORT_LED(5, 6, 1, 0, qsgmii)
SWITCH_PORT_LED(6, 7, 1, 0, qsgmii)
SWITCH_PORT_LED(7, 8, 1, 0, qsgmii)
SWITCH_PORT_LED(0, 1, 0, 0, 0, qsgmii)
SWITCH_PORT_LED(1, 2, 0, 1, 0, qsgmii)
SWITCH_PORT_LED(2, 3, 0, 2, 0, qsgmii)
SWITCH_PORT_LED(3, 4, 0, 3, 0, qsgmii)
SWITCH_PORT_LED(4, 5, 1, 0, 0, qsgmii)
SWITCH_PORT_LED(5, 6, 1, 1, 0, qsgmii)
SWITCH_PORT_LED(6, 7, 1, 2, 0, qsgmii)
SWITCH_PORT_LED(7, 8, 1, 3, 0, qsgmii)
SWITCH_PORT_LED(8, 9, 2, 0, usxgmii)
SWITCH_PORT_LED(9, 10, 2, 0, usxgmii)
SWITCH_PORT_LED(10, 11, 2, 0, usxgmii)
SWITCH_PORT_LED(11, 12, 2, 0, usxgmii)
SWITCH_PORT_LED(12, 13, 2, 0, usxgmii)
SWITCH_PORT_LED(13, 14, 2, 0, usxgmii)
SWITCH_PORT_LED(14, 15, 2, 0, usxgmii)
SWITCH_PORT_LED(15, 16, 2, 0, usxgmii)
SWITCH_PORT_LED(8, 9, 2, 0, 0, usxgmii)
SWITCH_PORT_LED(9, 10, 2, 1, 0, usxgmii)
SWITCH_PORT_LED(10, 11, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(11, 12, 2, 3, 0, usxgmii)
SWITCH_PORT_LED(12, 13, 2, 4, 0, usxgmii)
SWITCH_PORT_LED(13, 14, 2, 5, 0, usxgmii)
SWITCH_PORT_LED(14, 15, 2, 6, 0, usxgmii)
SWITCH_PORT_LED(15, 16, 2, 7, 0, usxgmii)
SWITCH_PORT_LED(16, 17, 3, 0, usxgmii)
SWITCH_PORT_LED(17, 18, 3, 0, usxgmii)
SWITCH_PORT_LED(18, 19, 3, 0, usxgmii)
SWITCH_PORT_LED(19, 20, 3, 0, usxgmii)
SWITCH_PORT_LED(20, 21, 3, 0, usxgmii)
SWITCH_PORT_LED(21, 22, 3, 0, usxgmii)
SWITCH_PORT_LED(22, 23, 3, 0, usxgmii)
SWITCH_PORT_LED(23, 24, 3, 0, usxgmii)
SWITCH_PORT_LED(16, 17, 3, 0, 0, usxgmii)
SWITCH_PORT_LED(17, 18, 3, 1, 0, usxgmii)
SWITCH_PORT_LED(18, 19, 3, 2, 0, usxgmii)
SWITCH_PORT_LED(19, 20, 3, 3, 0, usxgmii)
SWITCH_PORT_LED(20, 21, 3, 4, 0, usxgmii)
SWITCH_PORT_LED(21, 22, 3, 5, 0, usxgmii)
SWITCH_PORT_LED(22, 23, 3, 6, 0, usxgmii)
SWITCH_PORT_LED(23, 24, 3, 7, 0, usxgmii)
SWITCH_PORT_SFP(24, 25, 4, 1, 0)
SWITCH_PORT_SFP(25, 26, 6, 1, 1)

16
target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi
View File

@ -149,14 +149,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 2, 10g-qxgmii)
SWITCH_PORT_SDS(1, 2, 2, 10g-qxgmii)
SWITCH_PORT_SDS(2, 3, 2, 10g-qxgmii)
SWITCH_PORT_SDS(3, 4, 2, 10g-qxgmii)
SWITCH_PORT_SDS(8, 5, 3, 10g-qxgmii)
SWITCH_PORT_SDS(9, 6, 3, 10g-qxgmii)
SWITCH_PORT_SDS(10, 7, 3, 10g-qxgmii)
SWITCH_PORT_SDS(11, 8, 3, 10g-qxgmii)
SWITCH_PORT_SDS(0, 1, 2, 0, 10g-qxgmii)
SWITCH_PORT_SDS(1, 2, 2, 1, 10g-qxgmii)
SWITCH_PORT_SDS(2, 3, 2, 2, 10g-qxgmii)
SWITCH_PORT_SDS(3, 4, 2, 3, 10g-qxgmii)
SWITCH_PORT_SDS(8, 5, 3, 0, 10g-qxgmii)
SWITCH_PORT_SDS(9, 6, 3, 1, 10g-qxgmii)
SWITCH_PORT_SDS(10, 7, 3, 2, 10g-qxgmii)
SWITCH_PORT_SDS(11, 8, 3, 3, 10g-qxgmii)
/* CPU-port */
port@28 {

4
target/linux/realtek/dts/rtl9302_plasmacloud_mcx3.dts
View File

@ -164,8 +164,8 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 2, 2, 10g-qxgmii)
SWITCH_PORT_SDS(1, 1, 2, 10g-qxgmii)
SWITCH_PORT_SDS(0, 2, 2, 0, 10g-qxgmii)
SWITCH_PORT_SDS(1, 1, 2, 1, 10g-qxgmii)
SWITCH_PORT_SFP(26, 3, 8, 0, 0)

28
target/linux/realtek/dts/rtl9302_xikestor_sks8300-12e2t2x.dts
View File

@ -186,23 +186,23 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 2, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(1, 1, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(2, 4, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(3, 3, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(0, 2, 2, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(1, 1, 2, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(2, 4, 2, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(3, 3, 2, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(8, 6, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(9, 5, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(10, 8, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(11, 7, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(8, 6, 3, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(9, 5, 3, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(10, 8, 3, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(11, 7, 3, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(16, 10, 4, 0, 10g-qxgmii)
SWITCH_PORT_LED(17, 9, 4, 0, 10g-qxgmii)
SWITCH_PORT_LED(18, 12, 4, 0, 10g-qxgmii)
SWITCH_PORT_LED(19, 11, 4, 0, 10g-qxgmii)
SWITCH_PORT_LED(16, 10, 4, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(17, 9, 4, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(18, 12, 4, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(19, 11, 4, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(24, 13, 6, 1, usxgmii)
SWITCH_PORT_LED(25, 14, 7, 1, usxgmii)
SWITCH_PORT_LED(24, 13, 6, 0, 1, usxgmii)
SWITCH_PORT_LED(25, 14, 7, 0, 1, usxgmii)
SWITCH_PORT_SFP(26, 15, 8, 1, 0)
SWITCH_PORT_SFP(27, 16, 9, 1, 1)

22
target/linux/realtek/dts/rtl9302_zyxel_xgs1250-12-common.dtsi
View File

@ -253,18 +253,18 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 1, 2, 0, usxgmii)
SWITCH_PORT_LED(1, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(2, 3, 2, 0, usxgmii)
SWITCH_PORT_LED(3, 4, 2, 0, usxgmii)
SWITCH_PORT_LED(4, 5, 2, 0, usxgmii)
SWITCH_PORT_LED(5, 6, 2, 0, usxgmii)
SWITCH_PORT_LED(6, 7, 2, 0, usxgmii)
SWITCH_PORT_LED(7, 8, 2, 0, usxgmii)
SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
SWITCH_PORT_LED(1, 2, 2, 1, 0, usxgmii)
SWITCH_PORT_LED(2, 3, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(3, 4, 2, 3, 0, usxgmii)
SWITCH_PORT_LED(4, 5, 2, 4, 0, usxgmii)
SWITCH_PORT_LED(5, 6, 2, 5, 0, usxgmii)
SWITCH_PORT_LED(6, 7, 2, 6, 0, usxgmii)
SWITCH_PORT_LED(7, 8, 2, 7, 0, usxgmii)
SWITCH_PORT_LED(24, 9, 6, 1, usxgmii)
SWITCH_PORT_LED(25, 10, 7, 1, usxgmii)
SWITCH_PORT_LED(26, 11, 8, 1, usxgmii)
SWITCH_PORT_LED(24, 9, 6, 0, 1, usxgmii)
SWITCH_PORT_LED(25, 10, 7, 0, 1, usxgmii)
SWITCH_PORT_LED(26, 11, 8, 0, 1, usxgmii)
SWITCH_PORT_SFP(27, 12, 9, 2, 0)

20
target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
View File

@ -107,19 +107,19 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 1, 2, 0, usxgmii)
SWITCH_PORT_LED(1, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(2, 3, 2, 0, usxgmii)
SWITCH_PORT_LED(3, 4, 2, 0, usxgmii)
SWITCH_PORT_LED(4, 5, 2, 0, usxgmii)
SWITCH_PORT_LED(5, 6, 2, 0, usxgmii)
SWITCH_PORT_LED(6, 7, 2, 0, usxgmii)
SWITCH_PORT_LED(7, 8, 2, 0, usxgmii)
SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
SWITCH_PORT_LED(1, 2, 2, 1, 0, usxgmii)
SWITCH_PORT_LED(2, 3, 2, 2, 0, usxgmii)
SWITCH_PORT_LED(3, 4, 2, 3, 0, usxgmii)
SWITCH_PORT_LED(4, 5, 2, 4, 0, usxgmii)
SWITCH_PORT_LED(5, 6, 2, 5, 0, usxgmii)
SWITCH_PORT_LED(6, 7, 2, 6, 0, usxgmii)
SWITCH_PORT_LED(7, 8, 2, 7, 0, usxgmii)
port@24 {
reg = <24>;
label = "lan9";
pcs-handle = <&serdes6>;
pcs-handle = <&serdes6 0>;
phy-handle = <&phy24>;
phy-mode = "sgmii";
led-set = <1>;
@ -128,7 +128,7 @@
port@25 {
reg = <25>;
label = "lan10";
pcs-handle = <&serdes7>;
pcs-handle = <&serdes7 0>;
phy-handle = <&phy25>;
phy-mode = "sgmii";
led-set = <1>;

16
target/linux/realtek/dts/rtl9302_zyxel_xmg1915.dtsi
View File

@ -259,14 +259,14 @@
#size-cells = <0>;
/* Copper ports */
SWITCH_PORT_LED(0, 1, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(1, 2, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(2, 3, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(3, 4, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(8, 5, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(9, 6, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(10, 7, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(11, 8, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(0, 1, 2, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(1, 2, 2, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(2, 3, 2, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(3, 4, 2, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(8, 5, 3, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(9, 6, 3, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(10, 7, 3, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(11, 8, 3, 3, 0, 10g-qxgmii)
/* SFP cages */
SWITCH_PORT_SFP(25, 9, 7, 1, 0)

16
target/linux/realtek/dts/rtl9303_hasivo_s1100w-8xgt-se.dts
View File

@ -149,14 +149,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 1, 2, 0, usxgmii)
SWITCH_PORT_LED(8, 2, 3, 0, usxgmii)
SWITCH_PORT_LED(16, 3, 4, 0, usxgmii)
SWITCH_PORT_LED(20, 4, 5, 0, usxgmii)
SWITCH_PORT_LED(24, 5, 6, 0, usxgmii)
SWITCH_PORT_LED(25, 6, 7, 0, usxgmii)
SWITCH_PORT_LED(26, 7, 8, 0, usxgmii)
SWITCH_PORT_LED(27, 8, 9, 0, usxgmii)
SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii)
SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii)
SWITCH_PORT_LED(20, 4, 5, 0, 0, usxgmii)
SWITCH_PORT_LED(24, 5, 6, 0, 0, usxgmii)
SWITCH_PORT_LED(25, 6, 7, 0, 0, usxgmii)
SWITCH_PORT_LED(26, 7, 8, 0, 0, usxgmii)
SWITCH_PORT_LED(27, 8, 9, 0, 0, usxgmii)
/* Internal SoC */
port@28 {

16
target/linux/realtek/dts/rtl9303_hasivo_s1100wp-8gt-se.dts
View File

@ -196,7 +196,7 @@
port@0 {
reg = <0>;
label = "lan1";
pcs-handle = <&serdes2>;
pcs-handle = <&serdes2 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -206,7 +206,7 @@
port@8 {
reg = <8>;
label = "lan2";
pcs-handle = <&serdes3>;
pcs-handle = <&serdes3 0>;
phy-handle = <&phy8>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -216,7 +216,7 @@
port@16 {
reg = <16>;
label = "lan3";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-handle = <&phy16>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -226,7 +226,7 @@
port@20 {
reg = <20>;
label = "lan4";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-handle = <&phy20>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -236,7 +236,7 @@
port@24 {
reg = <24>;
label = "lan5";
pcs-handle = <&serdes6>;
pcs-handle = <&serdes6 0>;
phy-handle = <&phy24>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -246,7 +246,7 @@
port@25 {
reg = <25>;
label = "lan6";
pcs-handle = <&serdes7>;
pcs-handle = <&serdes7 0>;
phy-handle = <&phy25>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -256,7 +256,7 @@
port@26 {
reg = <26>;
label = "lan7";
pcs-handle = <&serdes8>;
pcs-handle = <&serdes8 0>;
phy-handle = <&phy26>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -266,7 +266,7 @@
port@27 {
reg = <27>;
label = "lan8";
pcs-handle = <&serdes9>;
pcs-handle = <&serdes9 0>;
phy-handle = <&phy27>;
phy-mode = "sgmii";
managed = "in-band-status";

10
target/linux/realtek/dts/rtl9303_hasivo_s600wp-5gt-2sx-se.dts
View File

@ -245,7 +245,7 @@
port@0 {
reg = <0>;
label = "lan1";
pcs-handle = <&serdes2>;
pcs-handle = <&serdes2 0>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -255,7 +255,7 @@
port@8 {
reg = <8>;
label = "lan2";
pcs-handle = <&serdes3>;
pcs-handle = <&serdes3 0>;
phy-handle = <&phy8>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -265,7 +265,7 @@
port@16 {
reg = <16>;
label = "lan3";
pcs-handle = <&serdes4>;
pcs-handle = <&serdes4 0>;
phy-handle = <&phy16>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -275,7 +275,7 @@
port@20 {
reg = <20>;
label = "lan4";
pcs-handle = <&serdes5>;
pcs-handle = <&serdes5 0>;
phy-handle = <&phy20>;
phy-mode = "sgmii";
managed = "in-band-status";
@ -285,7 +285,7 @@
port@24 {
reg = <24>;
label = "lan5";
pcs-handle = <&serdes6>;
pcs-handle = <&serdes6 0>;
phy-handle = <&phy24>;
phy-mode = "sgmii";
managed = "in-band-status";

8
target/linux/realtek/dts/rtl9303_xikestor_sks7300-4x4t.dts
View File

@ -259,10 +259,10 @@
SWITCH_PORT_SFP(16, 3, 4, 0, 2)
SWITCH_PORT_SFP(20, 4, 5, 0, 3)
SWITCH_PORT_SDS(24, 8, 6, usxgmii)
SWITCH_PORT_SDS(25, 7, 7, usxgmii)
SWITCH_PORT_SDS(26, 6, 8, usxgmii)
SWITCH_PORT_SDS(27, 5, 9, usxgmii)
SWITCH_PORT_SDS(24, 8, 6, 0, usxgmii)
SWITCH_PORT_SDS(25, 7, 7, 0, usxgmii)
SWITCH_PORT_SDS(26, 6, 8, 0, usxgmii)
SWITCH_PORT_SDS(27, 5, 9, 0, usxgmii)
port@28 {
ethernet = <&ethernet0>;

16
target/linux/realtek/dts/rtl9303_xikestor_sks8300-8t.dts
View File

@ -153,14 +153,14 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 2, usxgmii)
SWITCH_PORT_SDS(8, 2, 3, usxgmii)
SWITCH_PORT_SDS(16, 3, 4, usxgmii)
SWITCH_PORT_SDS(20, 4, 5, usxgmii)
SWITCH_PORT_SDS(24, 5, 6, usxgmii)
SWITCH_PORT_SDS(25, 6, 7, usxgmii)
SWITCH_PORT_SDS(26, 7, 8, usxgmii)
SWITCH_PORT_SDS(27, 8, 9, usxgmii)
SWITCH_PORT_SDS(0, 1, 2, 0, usxgmii)
SWITCH_PORT_SDS(8, 2, 3, 0, usxgmii)
SWITCH_PORT_SDS(16, 3, 4, 0, usxgmii)
SWITCH_PORT_SDS(20, 4, 5, 0, usxgmii)
SWITCH_PORT_SDS(24, 5, 6, 0, usxgmii)
SWITCH_PORT_SDS(25, 6, 7, 0, usxgmii)
SWITCH_PORT_SDS(26, 7, 8, 0, usxgmii)
SWITCH_PORT_SDS(27, 8, 9, 0, usxgmii)
port@28 {
ethernet = <&ethernet0>;

24
target/linux/realtek/dts/rtl930x.dtsi
View File

@ -252,51 +252,51 @@
serdes0: serdes@0 {
reg = <0>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes1: serdes@1 {
reg = <1>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes2: serdes@2 {
reg = <2>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes3: serdes@3 {
reg = <3>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes4: serdes@4 {
reg = <4>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes5: serdes@5 {
reg = <5>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes6: serdes@6 {
reg = <6>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes7: serdes@7 {
reg = <7>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes8: serdes@8 {
reg = <8>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes9: serdes@9 {
reg = <9>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes10: serdes@10 {
reg = <10>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes11: serdes@11 {
reg = <11>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
};

96
target/linux/realtek/dts/rtl9311_linksys_lgs352c.dts
View File

@ -140,59 +140,59 @@
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 2, usxgmii)
SWITCH_PORT_SDS(1, 2, 2, usxgmii)
SWITCH_PORT_SDS(2, 3, 2, usxgmii)
SWITCH_PORT_SDS(3, 4, 2, usxgmii)
SWITCH_PORT_SDS(4, 5, 2, usxgmii)
SWITCH_PORT_SDS(5, 6, 2, usxgmii)
SWITCH_PORT_SDS(6, 7, 2, usxgmii)
SWITCH_PORT_SDS(7, 8, 2, usxgmii)
SWITCH_PORT_SDS(0, 1, 2, 0, usxgmii)
SWITCH_PORT_SDS(1, 2, 2, 1, usxgmii)
SWITCH_PORT_SDS(2, 3, 2, 2, usxgmii)
SWITCH_PORT_SDS(3, 4, 2, 3, usxgmii)
SWITCH_PORT_SDS(4, 5, 2, 4, usxgmii)
SWITCH_PORT_SDS(5, 6, 2, 5, usxgmii)
SWITCH_PORT_SDS(6, 7, 2, 6, usxgmii)
SWITCH_PORT_SDS(7, 8, 2, 7, usxgmii)
SWITCH_PORT_SDS(8, 9, 3, usxgmii)
SWITCH_PORT_SDS(9, 10, 3, usxgmii)
SWITCH_PORT_SDS(10, 11, 3, usxgmii)
SWITCH_PORT_SDS(11, 12, 3, usxgmii)
SWITCH_PORT_SDS(12, 13, 3, usxgmii)
SWITCH_PORT_SDS(13, 14, 3, usxgmii)
SWITCH_PORT_SDS(14, 15, 3, usxgmii)
SWITCH_PORT_SDS(15, 16, 3, usxgmii)
SWITCH_PORT_SDS(8, 9, 3, 0, usxgmii)
SWITCH_PORT_SDS(9, 10, 3, 1, usxgmii)
SWITCH_PORT_SDS(10, 11, 3, 2, usxgmii)
SWITCH_PORT_SDS(11, 12, 3, 3, usxgmii)
SWITCH_PORT_SDS(12, 13, 3, 4, usxgmii)
SWITCH_PORT_SDS(13, 14, 3, 5, usxgmii)
SWITCH_PORT_SDS(14, 15, 3, 6, usxgmii)
SWITCH_PORT_SDS(15, 16, 3, 7, usxgmii)
SWITCH_PORT_SDS(16, 17, 4, usxgmii)
SWITCH_PORT_SDS(17, 18, 4, usxgmii)
SWITCH_PORT_SDS(18, 19, 4, usxgmii)
SWITCH_PORT_SDS(19, 20, 4, usxgmii)
SWITCH_PORT_SDS(20, 21, 4, usxgmii)
SWITCH_PORT_SDS(21, 22, 4, usxgmii)
SWITCH_PORT_SDS(22, 23, 4, usxgmii)
SWITCH_PORT_SDS(23, 24, 4, usxgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, usxgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, usxgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, usxgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, usxgmii)
SWITCH_PORT_SDS(20, 21, 4, 4, usxgmii)
SWITCH_PORT_SDS(21, 22, 4, 5, usxgmii)
SWITCH_PORT_SDS(22, 23, 4, 6, usxgmii)
SWITCH_PORT_SDS(23, 24, 4, 7, usxgmii)
SWITCH_PORT_SDS(24, 25, 5, usxgmii)
SWITCH_PORT_SDS(25, 26, 5, usxgmii)
SWITCH_PORT_SDS(26, 27, 5, usxgmii)
SWITCH_PORT_SDS(27, 28, 5, usxgmii)
SWITCH_PORT_SDS(28, 29, 5, usxgmii)
SWITCH_PORT_SDS(29, 30, 5, usxgmii)
SWITCH_PORT_SDS(30, 31, 5, usxgmii)
SWITCH_PORT_SDS(31, 32, 5, usxgmii)
SWITCH_PORT_SDS(24, 25, 5, 0, usxgmii)
SWITCH_PORT_SDS(25, 26, 5, 1, usxgmii)
SWITCH_PORT_SDS(26, 27, 5, 2, usxgmii)
SWITCH_PORT_SDS(27, 28, 5, 3, usxgmii)
SWITCH_PORT_SDS(28, 29, 5, 4, usxgmii)
SWITCH_PORT_SDS(29, 30, 5, 5, usxgmii)
SWITCH_PORT_SDS(30, 31, 5, 6, usxgmii)
SWITCH_PORT_SDS(31, 32, 5, 7, usxgmii)
SWITCH_PORT_SDS(32, 33, 6, usxgmii)
SWITCH_PORT_SDS(33, 34, 6, usxgmii)
SWITCH_PORT_SDS(34, 35, 6, usxgmii)
SWITCH_PORT_SDS(35, 36, 6, usxgmii)
SWITCH_PORT_SDS(36, 37, 6, usxgmii)
SWITCH_PORT_SDS(37, 38, 6, usxgmii)
SWITCH_PORT_SDS(38, 39, 6, usxgmii)
SWITCH_PORT_SDS(39, 40, 6, usxgmii)
SWITCH_PORT_SDS(32, 33, 6, 0, usxgmii)
SWITCH_PORT_SDS(33, 34, 6, 1, usxgmii)
SWITCH_PORT_SDS(34, 35, 6, 2, usxgmii)
SWITCH_PORT_SDS(35, 36, 6, 3, usxgmii)
SWITCH_PORT_SDS(36, 37, 6, 4, usxgmii)
SWITCH_PORT_SDS(37, 38, 6, 5, usxgmii)
SWITCH_PORT_SDS(38, 39, 6, 6, usxgmii)
SWITCH_PORT_SDS(39, 40, 6, 7, usxgmii)
SWITCH_PORT_SDS(40, 41, 7, usxgmii)
SWITCH_PORT_SDS(41, 42, 7, usxgmii)
SWITCH_PORT_SDS(42, 43, 7, usxgmii)
SWITCH_PORT_SDS(43, 44, 7, usxgmii)
SWITCH_PORT_SDS(44, 45, 7, usxgmii)
SWITCH_PORT_SDS(45, 46, 7, usxgmii)
SWITCH_PORT_SDS(46, 47, 7, usxgmii)
SWITCH_PORT_SDS(47, 48, 7, usxgmii)
SWITCH_PORT_SDS(40, 41, 7, 0, usxgmii)
SWITCH_PORT_SDS(41, 42, 7, 1, usxgmii)
SWITCH_PORT_SDS(42, 43, 7, 2, usxgmii)
SWITCH_PORT_SDS(43, 44, 7, 3, usxgmii)
SWITCH_PORT_SDS(44, 45, 7, 4, usxgmii)
SWITCH_PORT_SDS(45, 46, 7, 5, usxgmii)
SWITCH_PORT_SDS(46, 47, 7, 6, usxgmii)
SWITCH_PORT_SDS(47, 48, 7, 7, usxgmii)
SWITCH_PORT_SFP(48, 49, 8, 0, 0)
SWITCH_PORT_SFP(50, 50, 9, 0, 1)

53
target/linux/realtek/dts/rtl9312_plasmacloud_common.dtsi
View File

@ -275,30 +275,35 @@
#size-cells = <0>;
/* copper ethernet */
SWITCH_PORT_SDS(0, 1, 2, 10g-qxgmii)
SWITCH_PORT_SDS(1, 2, 2, 10g-qxgmii)
SWITCH_PORT_SDS(4, 3, 2, 10g-qxgmii)
SWITCH_PORT_SDS(5, 4, 2, 10g-qxgmii)
SWITCH_PORT_SDS(8, 5, 3, 10g-qxgmii)
SWITCH_PORT_SDS(9, 6, 3, 10g-qxgmii)
SWITCH_PORT_SDS(12, 7, 3, 10g-qxgmii)
SWITCH_PORT_SDS(13, 8, 3, 10g-qxgmii)
SWITCH_PORT_SDS(16, 9, 4, 10g-qxgmii)
SWITCH_PORT_SDS(17, 10, 4, 10g-qxgmii)
SWITCH_PORT_SDS(20, 11, 4, 10g-qxgmii)
SWITCH_PORT_SDS(21, 12, 4, 10g-qxgmii)
SWITCH_PORT_SDS(24, 13, 5, 10g-qxgmii)
SWITCH_PORT_SDS(25, 14, 5, 10g-qxgmii)
SWITCH_PORT_SDS(28, 15, 5, 10g-qxgmii)
SWITCH_PORT_SDS(29, 16, 5, 10g-qxgmii)
SWITCH_PORT_SDS(32, 17, 6, 10g-qxgmii)
SWITCH_PORT_SDS(33, 18, 6, 10g-qxgmii)
SWITCH_PORT_SDS(36, 19, 6, 10g-qxgmii)
SWITCH_PORT_SDS(37, 20, 6, 10g-qxgmii)
SWITCH_PORT_SDS(40, 21, 7, 10g-qxgmii)
SWITCH_PORT_SDS(41, 22, 7, 10g-qxgmii)
SWITCH_PORT_SDS(44, 23, 7, 10g-qxgmii)
SWITCH_PORT_SDS(45, 24, 7, 10g-qxgmii)
SWITCH_PORT_SDS(0, 1, 2, 0, 10g-qxgmii)
SWITCH_PORT_SDS(1, 2, 2, 1, 10g-qxgmii)
SWITCH_PORT_SDS(4, 3, 2, 2, 10g-qxgmii)
SWITCH_PORT_SDS(5, 4, 2, 3, 10g-qxgmii)
SWITCH_PORT_SDS(8, 5, 3, 0, 10g-qxgmii)
SWITCH_PORT_SDS(9, 6, 3, 1, 10g-qxgmii)
SWITCH_PORT_SDS(12, 7, 3, 2, 10g-qxgmii)
SWITCH_PORT_SDS(13, 8, 3, 3, 10g-qxgmii)
SWITCH_PORT_SDS(16, 9, 4, 0, 10g-qxgmii)
SWITCH_PORT_SDS(17, 10, 4, 1, 10g-qxgmii)
SWITCH_PORT_SDS(20, 11, 4, 2, 10g-qxgmii)
SWITCH_PORT_SDS(21, 12, 4, 3, 10g-qxgmii)
SWITCH_PORT_SDS(24, 13, 5, 0, 10g-qxgmii)
SWITCH_PORT_SDS(25, 14, 5, 1, 10g-qxgmii)
SWITCH_PORT_SDS(28, 15, 5, 2, 10g-qxgmii)
SWITCH_PORT_SDS(29, 16, 5, 3, 10g-qxgmii)
SWITCH_PORT_SDS(32, 17, 6, 0, 10g-qxgmii)
SWITCH_PORT_SDS(33, 18, 6, 1, 10g-qxgmii)
SWITCH_PORT_SDS(36, 19, 6, 2, 10g-qxgmii)
SWITCH_PORT_SDS(37, 20, 6, 3, 10g-qxgmii)
SWITCH_PORT_SDS(40, 21, 7, 0, 10g-qxgmii)
SWITCH_PORT_SDS(41, 22, 7, 1, 10g-qxgmii)
SWITCH_PORT_SDS(44, 23, 7, 2, 10g-qxgmii)
SWITCH_PORT_SDS(45, 24, 7, 3, 10g-qxgmii)
SWITCH_PORT_SFP(48, 25, 8, 1, 0)
SWITCH_PORT_SFP(50, 26, 9, 1, 1)

4
target/linux/realtek/dts/rtl9313_zyxel_xs1930-12f.dts
View File

@ -230,8 +230,8 @@
SWITCH_PORT_SFP(53, 10, 11, 1, 10)
/* Base-T ports */
SWITCH_PORT_LED(54, 11, 12, 0, usxgmii)
SWITCH_PORT_LED(55, 12, 13, 0, usxgmii)
SWITCH_PORT_LED(54, 11, 12, 0, 0, usxgmii)
SWITCH_PORT_LED(55, 12, 13, 0, 0, usxgmii)
/* CPU port */
port@56 {

4
target/linux/realtek/dts/rtl9313_zyxel_xs1930-12hp.dts
View File

@ -74,8 +74,8 @@
&switch0 {
ethernet-ports {
/* Copper ports behind AQR113C */
SWITCH_PORT_LED(52, 9, 10, 0, usxgmii)
SWITCH_PORT_LED(53, 10, 11, 0, usxgmii)
SWITCH_PORT_LED(52, 9, 10, 0, 0, usxgmii)
SWITCH_PORT_LED(53, 10, 11, 0, 0, usxgmii)
SWITCH_PORT_SFP(54, 11, 12, 0, 1)
SWITCH_PORT_SFP(55, 12, 13, 0, 2)

16
target/linux/realtek/dts/rtl9313_zyxel_xs1930-aqr813.dtsi
View File

@ -127,14 +127,14 @@
#size-cells = <0>;
/* Copper ports behind AQR813 */
SWITCH_PORT_LED(0, 1, 2, 0, usxgmii)
SWITCH_PORT_LED(8, 2, 3, 0, usxgmii)
SWITCH_PORT_LED(16, 3, 4, 0, usxgmii)
SWITCH_PORT_LED(24, 4, 5, 0, usxgmii)
SWITCH_PORT_LED(32, 5, 6, 0, usxgmii)
SWITCH_PORT_LED(40, 6, 7, 0, usxgmii)
SWITCH_PORT_LED(48, 7, 8, 0, usxgmii)
SWITCH_PORT_LED(50, 8, 9, 0, usxgmii)
SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii)
SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii)
SWITCH_PORT_LED(24, 4, 5, 0, 0, usxgmii)
SWITCH_PORT_LED(32, 5, 6, 0, 0, usxgmii)
SWITCH_PORT_LED(40, 6, 7, 0, 0, usxgmii)
SWITCH_PORT_LED(48, 7, 8, 0, 0, usxgmii)
SWITCH_PORT_LED(50, 8, 9, 0, 0, usxgmii)
/* CPU port */
port@56 {

28
target/linux/realtek/dts/rtl931x.dtsi
View File

@ -284,59 +284,59 @@
serdes0: serdes@0 {
reg = <0>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes1: serdes@1 {
reg = <1>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes2: serdes@2 {
reg = <2>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes3: serdes@3 {
reg = <3>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes4: serdes@4 {
reg = <4>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes5: serdes@5 {
reg = <5>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes6: serdes@6 {
reg = <6>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes7: serdes@7 {
reg = <7>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes8: serdes@8 {
reg = <8>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes9: serdes@9 {
reg = <9>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes10: serdes@10 {
reg = <10>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes11: serdes@11 {
reg = <11>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes12: serdes@12 {
reg = <12>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
serdes13: serdes@13 {
reg = <13>;
#pcs-cells = <0>;
#pcs-cells = <1>;
};
};