43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
184 lines
4.0 KiB
Plaintext
184 lines
4.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl9313_zyxel_xs1930.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/mux/mux.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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sfp_gpio_mux: gpio-mux {
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compatible = "gpio-mux";
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mux-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>,
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<&gpio0 14 GPIO_ACTIVE_HIGH>;
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#mux-control-cells = <0>;
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idle-state = <MUX_IDLE_AS_IS>;
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};
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sfp1_gpio: sfp-gpio-1 {
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compatible = "gpio-line-mux";
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gpio-controller;
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#gpio-cells = <2>;
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mux-controls = <&sfp_gpio_mux>;
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muxed-gpio = <&gpio0 19 GPIO_ACTIVE_HIGH>;
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gpio-line-names = "SFP1_LOS", "SFP1_MOD_ABS", "SFP1_TX_FAULT";
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gpio-line-mux-states = <0>, <1>, <3>;
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};
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sfp2_gpio: sfp-gpio-2 {
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compatible = "gpio-line-mux";
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gpio-controller;
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#gpio-cells = <2>;
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mux-controls = <&sfp_gpio_mux>;
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muxed-gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
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gpio-line-names = "SFP2_LOS", "SFP2_MOD_ABS", "SFP2_TX_FAULT";
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gpio-line-mux-states = <0>, <1>, <3>;
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};
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sfp1: sfp-p1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&sfp1_gpio 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&sfp1_gpio 1 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&sfp1_gpio 2 GPIO_ACTIVE_HIGH>;
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};
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sfp2: sfp-p2 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&sfp2_gpio 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&sfp2_gpio 1 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&sfp2_gpio 2 GPIO_ACTIVE_HIGH>;
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};
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};
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&gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_jtag>;
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/*
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* GPIO 31 is the global reset pin shared by all PHYs across all MDIO
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* buses. It is intentionally not declared as reset-gpios on any bus:
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* the MDIO driver / phylink only support a reset GPIO per bus, not on
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* the parent controller. Attaching it to a single bus would still reset
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* the PHYs on the other buses as a side effect, leaving their software
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* state out of sync with the hardware and likely breaking them.
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*/
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phy_reset_hog {
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gpio-hog;
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gpios = <31 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "phy-reset";
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};
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sfp_enable_hog {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_LOW>,
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<7 GPIO_ACTIVE_LOW>;
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output-high;
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line-name = "sfp-enable";
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};
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};
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&i2c_mst1 {
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status = "okay";
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i2c0: i2c@0 {
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reg = <0>;
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};
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i2c1: i2c@1 {
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reg = <1>;
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};
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i2c2: i2c@2 {
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reg = <2>;
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lm96000: lm96000@2e {
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compatible = "national,lm85";
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reg = <0x2e>;
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};
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};
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};
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&mdio_bus0 {
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/* AQR813 */
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PHY_C45(0, 8)
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PHY_C45(8, 9)
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PHY_C45(16, 10)
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PHY_C45(24, 11)
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PHY_C45(32, 12)
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PHY_C45(40, 13)
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PHY_C45(48, 14)
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PHY_C45(50, 15)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Copper ports behind AQR813 */
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SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
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SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii)
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SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii)
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SWITCH_PORT_LED(24, 4, 5, 0, 0, usxgmii)
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SWITCH_PORT_LED(32, 5, 6, 0, 0, usxgmii)
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SWITCH_PORT_LED(40, 6, 7, 0, 0, usxgmii)
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SWITCH_PORT_LED(48, 7, 8, 0, 0, usxgmii)
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SWITCH_PORT_LED(50, 8, 9, 0, 0, usxgmii)
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/* CPU port */
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port@56 {
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ethernet = <ðernet0>;
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reg = <56>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&port0 { managed = "in-band-status"; };
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&port8 { managed = "in-band-status"; };
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&port16 { managed = "in-band-status"; };
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&port24 { managed = "in-band-status"; };
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&port32 { managed = "in-band-status"; };
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&port40 { managed = "in-band-status"; };
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&port48 { managed = "in-band-status"; };
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&port50 { managed = "in-band-status"; };
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&serdes6 {
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rx-polarity = <PHY_POL_INVERT>;
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes7 {
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rx-polarity = <PHY_POL_INVERT>;
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes8 {
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rx-polarity = <PHY_POL_INVERT>;
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes9 {
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rx-polarity = <PHY_POL_INVERT>;
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes12 { tx-polarity = <PHY_POL_INVERT>; };
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&serdes13 { tx-polarity = <PHY_POL_INVERT>; };
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