43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
248 lines
5.3 KiB
Plaintext
248 lines
5.3 KiB
Plaintext
/dts-v1/;
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#include "rtl839x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-leds";
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led_sys: sys {
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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};
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locator {
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gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
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function = LED_FUNCTION_INDICATOR;
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color = <LED_COLOR_ID_BLUE>;
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};
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};
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/* i2c of port 25 SFP cage */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p25 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 23 GPIO_ACTIVE_LOW>;
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tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of port 26 SFP cage */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p26 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 17 GPIO_ACTIVE_LOW>;
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tx-fault-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of port 27 SFP cage */
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i2c2: i2c-gpio-2 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp2: sfp-p27 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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los-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 13 GPIO_ACTIVE_LOW>;
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tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of port 28 SFP cage */
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i2c3: i2c-gpio-3 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp3: sfp-p28 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c3>;
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los-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 20 GPIO_ACTIVE_LOW>;
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tx-fault-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
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};
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/* i2c for hwmon/PoE */
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i2c4: i2c-gpio-4 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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flash_partitions: partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootbase";
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reg = <0x0 0x20000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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factory_macaddr: macaddr@1fff8 {
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reg = <0x1fff8 0x6>;
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};
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};
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&factory_macaddr>;
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nvmem-cell-names = "mac-address";
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};
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&mdio_bus0 {
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/* External phy RTL8218B #1 */
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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/* External phy RTL8218B #2 */
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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/* External phy RTL8218B #3 */
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
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SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
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SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
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SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
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SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
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SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
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SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
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SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
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SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
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SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
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SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
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SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
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SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
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SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
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SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
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SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
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SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
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/* CPU-Port */
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port@52 {
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ethernet = <ðernet0>;
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reg = <52>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&mdio_aux {
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status = "okay";
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gpio1: expander@3 {
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compatible = "realtek,rtl8231";
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reg = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio1 0 0 37>;
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led-controller {
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compatible = "realtek,rtl8231-leds";
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status = "disabled";
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};
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};
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};
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