43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
149 lines
2.8 KiB
Plaintext
149 lines
2.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl8382_hpe_1920.dtsi"
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/ {
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compatible = "hpe,1920-16g", "realtek,rtl838x-soc";
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model = "HPE 1920-16G (JG923A)";
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
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SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
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SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
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SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
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SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
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SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
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SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
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SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
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SWITCH_PORT_SDS(24, 17, 4, 0, qsgmii)
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SWITCH_PORT_SDS(25, 18, 4, 1, qsgmii)
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SWITCH_PORT_SDS(26, 19, 4, 2, qsgmii)
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SWITCH_PORT_SDS(27, 20, 4, 3, qsgmii)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&port8 {
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nvmem-cells = <&macaddr_factory 2>;
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nvmem-cell-names = "mac-address";
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};
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&port9 {
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nvmem-cells = <&macaddr_factory 3>;
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nvmem-cell-names = "mac-address";
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};
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&port10 {
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nvmem-cells = <&macaddr_factory 4>;
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nvmem-cell-names = "mac-address";
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};
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&port11 {
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nvmem-cells = <&macaddr_factory 5>;
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nvmem-cell-names = "mac-address";
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};
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&port12 {
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nvmem-cells = <&macaddr_factory 6>;
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nvmem-cell-names = "mac-address";
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};
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&port13 {
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nvmem-cells = <&macaddr_factory 7>;
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nvmem-cell-names = "mac-address";
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};
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&port14 {
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nvmem-cells = <&macaddr_factory 8>;
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nvmem-cell-names = "mac-address";
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};
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&port15 {
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nvmem-cells = <&macaddr_factory 9>;
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nvmem-cell-names = "mac-address";
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};
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&port16 {
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nvmem-cells = <&macaddr_factory 10>;
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nvmem-cell-names = "mac-address";
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};
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&port17 {
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nvmem-cells = <&macaddr_factory 11>;
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nvmem-cell-names = "mac-address";
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};
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&port18 {
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nvmem-cells = <&macaddr_factory 12>;
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nvmem-cell-names = "mac-address";
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};
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&port19 {
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nvmem-cells = <&macaddr_factory 13>;
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nvmem-cell-names = "mac-address";
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};
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&port20 {
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nvmem-cells = <&macaddr_factory 14>;
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nvmem-cell-names = "mac-address";
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};
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&port21 {
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nvmem-cells = <&macaddr_factory 15>;
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nvmem-cell-names = "mac-address";
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};
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&port22 {
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nvmem-cells = <&macaddr_factory 16>;
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nvmem-cell-names = "mac-address";
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};
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&port23 {
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nvmem-cells = <&macaddr_factory 17>;
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nvmem-cell-names = "mac-address";
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};
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&port24 {
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nvmem-cells = <&macaddr_factory 18>;
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nvmem-cell-names = "mac-address";
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};
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&port25 {
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nvmem-cells = <&macaddr_factory 19>;
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nvmem-cell-names = "mac-address";
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};
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&port26 {
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nvmem-cells = <&macaddr_factory 20>;
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nvmem-cell-names = "mac-address";
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};
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&port27 {
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nvmem-cells = <&macaddr_factory 21>;
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nvmem-cell-names = "mac-address";
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};
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