43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
152 lines
3.5 KiB
Plaintext
152 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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led-boot = &led_pwr_sys;
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led-failsafe = &led_pwr_sys;
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led-running = &led_pwr_sys;
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led-upgrade = &led_pwr_sys;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_pwr_sys: led-0 {
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label = "green:power";
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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sfp0: sfp-p11 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p12 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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led_set: led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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/* [Green] [Amber] */
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led_set0 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)>;
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/* [Amber] [Lime] [Green] [Blue] */
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led_set1 = <(RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M | RTL93XX_LED_SET_LINK |
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RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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/* [Lime] [Blue] */
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led_set2 = <(RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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};
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};
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&i2c_mst1 {
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status = "okay";
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/* i2c of the left SFP+ cage seen from the front; port 11 */
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i2c0: i2c@0 {
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reg = <0>;
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};
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/* i2c of the right SFP+ cage seen from the front; port 12 */
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i2c1: i2c@1 {
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reg = <1>;
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};
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};
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&mdio_bus0 {
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/*
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* External RTL8218D PHY
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*
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* reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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* disabled because we do not know how to bring up again
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*/
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
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SWITCH_PORT_LED(1, 2, 2, 1, 0, usxgmii)
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SWITCH_PORT_LED(2, 3, 2, 2, 0, usxgmii)
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SWITCH_PORT_LED(3, 4, 2, 3, 0, usxgmii)
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SWITCH_PORT_LED(4, 5, 2, 4, 0, usxgmii)
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SWITCH_PORT_LED(5, 6, 2, 5, 0, usxgmii)
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SWITCH_PORT_LED(6, 7, 2, 6, 0, usxgmii)
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SWITCH_PORT_LED(7, 8, 2, 7, 0, usxgmii)
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port@24 {
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reg = <24>;
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label = "lan9";
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pcs-handle = <&serdes6 0>;
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phy-handle = <&phy24>;
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phy-mode = "sgmii";
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led-set = <1>;
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managed = "in-band-status";
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};
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port@25 {
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reg = <25>;
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label = "lan10";
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pcs-handle = <&serdes7 0>;
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phy-handle = <&phy25>;
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phy-mode = "sgmii";
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led-set = <1>;
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managed = "in-band-status";
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};
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SWITCH_PORT_SFP(26, 11, 8, 2, 0)
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SWITCH_PORT_SFP(27, 12, 9, 2, 1)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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