43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
135 lines
2.4 KiB
Plaintext
135 lines
2.4 KiB
Plaintext
/dts-v1/;
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#include "rtl839x_zyxel_gs1920-24hp-common.dtsi"
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/ {
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compatible = "zyxel,gs1920-24hp-v2", "realtek,rtl8391-soc";
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model = "Zyxel GS1920-24HPv2";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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cloud-amber {
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gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
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color = <LED_COLOR_ID_AMBER>;
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};
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pwr-green {
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gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_GREEN>;
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default-state = "on";
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};
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pwr-amber {
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gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_AMBER>;
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};
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poe-max {
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gpios = <&gpio1 35 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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};
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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restore {
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label = "restore";
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gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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linux,input-type = <EV_KEY>;
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};
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};
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/delete-node/ i2c-gpio-0;
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/delete-node/ i2c-gpio-1;
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i2c-gpio-shared {
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compatible = "i2c-gpio-shared";
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scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c0: i2c@0 {
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sda-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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i2c1: i2c@1 {
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sda-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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};
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};
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&i2c2 {
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scl-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&i2c3 {
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scl-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&i2c4 {
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lm96000: lm96000@2e {
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compatible = "national,lm85";
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reg = <0x2e>;
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};
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};
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&flash_partitions {
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partition@20000 {
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label = "reserved";
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reg = <0x20000 0x1e0000>;
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read-only;
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};
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partition@200000 {
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reg = <0x200000 0x1e00000>;
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label = "factory";
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "loader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "firmware";
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reg = <0x10000 0x1d00000>;
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compatible = "openwrt,uimage", "denx,uimage";
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};
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};
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};
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&mdio_bus0 {
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/* External phy RTL8214FC #1 */
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PHY_C22_SFP(24, 24, 0)
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PHY_C22_SFP(25, 25, 1)
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PHY_C22_SFP(26, 26, 2)
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PHY_C22_SFP(27, 27, 3)
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};
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&switch0 {
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ethernet-ports {
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SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
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SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
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SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
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SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
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};
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};
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