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openwrt/target/linux/realtek/dts/rtl8393_panasonic_m48eg-pn28480k.dts
Jonas Jelonek 43562f97e7
realtek: dts: add link index cell to pcs-handle phandles 
A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.

The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.

Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.

No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.

Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-05-31 12:52:40 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rtl839x.dtsi"
#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "panasonic,m48eg-pn28480k", "realtek,rtl8393-soc";
model = "Panasonic Switch-M48eG PN28480K";
aliases {
led-boot = &led_status_eco_green;
led-failsafe = &led_status_eco_amber;
led-running = &led_status_eco_green;
led-upgrade = &led_status_eco_green;
};
fan: gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
/* the actual speeds (rpm) are unknown, just use dummy values */
gpio-fan,speed-map = <1 0>, <2 1>;
#cooling-cells = <2>;
};
/*
* sfp0/1/2/3 are "combo" port with each TP port (45/46/47/48),
* and they are connected to the RTL8218FB. Currently, there is
* no support for the chip and only TP ports work by the RTL8218B
* support.
*/
sfp0: sfp-p45 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
sfp1: sfp-p46 {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
sfp2: sfp-p47 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
tx-fault-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
sfp3: sfp-p48 {
compatible = "sff,sfp";
i2c-bus = <&i2c3>;
tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
};
thermal-zones {
/*
* Zone for SoC temperature
*
* Fan speed:
*
* - 0-44 celsius: Low
* - 45-54 celsius: High
*/
cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <2000>;
thermal-sensors = <&tsens_soc>;
trips {
cpu_alert: trip-point {
temperature = <45000>;
hysteresis = <4000>;
type = "active";
};
cpu_crit {
temperature = <55000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map {
trip = <&cpu_alert>;
cooling-device = <&fan 0 1>;
};
};
};
/*
* Zone for system temperature
*
* Fan speed:
*
* - 0-39 celsius: Low
* - 40-49 celsius: High
*
* Note: official recommended ranges of temperature on each
* fan speed setting:
*
* - Low speed : 0-40 celsius
* - High speed: 0-50 celsius
*
* (stock firmware doesn't support auto-selection of
* speed and need to be selected manually by user)
*/
sys-thermal {
polling-delay-passive = <1000>;
polling-delay = <2000>;
thermal-sensors = <&tsens_sys>;
trips {
sys_alert: trip-point {
temperature = <40000>;
hysteresis = <4000>;
type = "active";
};
sys_crit {
temperature = <50000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map {
trip = <&sys_alert>;
cooling-device = <&fan 0 1>;
};
};
};
};
};
&leds {
led_status_eco_amber: led-5 {
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
};
led_status_eco_green: led-6 {
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
};
};
&i2c_gpio_0 {
scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* Microchip TCN75A (for SoC) */
tsens_soc: sensor@48 {
compatible = "microchip,tcn75";
reg = <0x48>;
#thermal-sensor-cells = <0>;
};
/* Microchip TCN75A (for System) */
tsens_sys: sensor@49 {
compatible = "microchip,tcn75";
reg = <0x49>;
#thermal-sensor-cells = <0>;
};
};
&i2c_gpio_1 {
scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&gpio2 {
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio0>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
/*
* GPIO12 (IO1_4): 5x RTL8218B + RTL8218FB
*
* This GPIO pin should be specified as "reset-gpio" in mdio node,
* but the current configuration of RTL8218B phy in the phy driver
* seems to be incomplete and RTL8218FB phy won't be configured on
* RTL8218D support. So, ethernet ports on these phys will be broken
* after hard-resetting.
* (RTL8218FB phy will be detected as RTL8218D by the phy driver)
* At the moment, configure this GPIO pin as gpio-hog to avoid breaking
* by resetting.
*/
ext_switch_reset {
gpio-hog;
gpios = <12 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "ext-switch-reset";
};
};
&i2c_switch {
i2c0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
&mdio_bus0 {
PHY_C22(0, 0)
PHY_C22(1, 1)
PHY_C22(2, 2)
PHY_C22(3, 3)
PHY_C22(4, 4)
PHY_C22(5, 5)
PHY_C22(6, 6)
PHY_C22(7, 7)
PHY_C22(8, 8)
PHY_C22(9, 9)
PHY_C22(10, 10)
PHY_C22(11, 11)
PHY_C22(12, 12)
PHY_C22(13, 13)
PHY_C22(14, 14)
PHY_C22(15, 15)
PHY_C22(16, 16)
PHY_C22(17, 17)
PHY_C22(18, 18)
PHY_C22(19, 19)
PHY_C22(20, 20)
PHY_C22(21, 21)
PHY_C22(22, 22)
PHY_C22(23, 23)
};
&mdio_bus1 {
PHY_C22(24, 0)
PHY_C22(25, 1)
PHY_C22(26, 2)
PHY_C22(27, 3)
PHY_C22(28, 4)
PHY_C22(29, 5)
PHY_C22(30, 6)
PHY_C22(31, 7)
PHY_C22(32, 8)
PHY_C22(33, 9)
PHY_C22(34, 10)
PHY_C22(35, 11)
PHY_C22(36, 12)
PHY_C22(37, 13)
PHY_C22(38, 14)
PHY_C22(39, 15)
/* RTL8218FB */
PHY_C22(40, 16)
PHY_C22(41, 17)
PHY_C22(42, 18)
PHY_C22(43, 19)
PHY_C22(44, 20)
PHY_C22(45, 21)
PHY_C22(46, 22)
PHY_C22(47, 23)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
port@52 {
ethernet = <&ethernet0>;
reg = <52>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
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