43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
119 lines
2.5 KiB
Plaintext
119 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl8393_hpe_1920.dtsi"
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/ {
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compatible = "hpe,1920-48g", "realtek,rtl8393-soc";
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model = "HPE 1920-48G (JG927A)";
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i2c-gpio-shared0 {
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compatible = "i2c-gpio-shared";
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scl-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c0: i2c@0 {
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sda-gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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i2c2: i2c@2 {
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sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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};
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i2c-gpio-shared1 {
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compatible = "i2c-gpio-shared";
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scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c1: i2c@1 {
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sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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i2c3: i2c@3 {
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sda-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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};
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sfp0: sfp-p49 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 19 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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sfp1: sfp-p50 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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sfp2: sfp-p51 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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los-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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sfp3: sfp-p52 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c3>;
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los-gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 15 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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};
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&mdio_bus1 {
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PHY_C22_SFP(48, 24, 1)
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PHY_C22_SFP(49, 25, 3)
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PHY_C22_SFP(50, 26, 0)
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PHY_C22_SFP(51, 27, 2)
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};
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&switch0 {
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ethernet-ports {
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SWITCH_PORT_SDS(48, 50, 12, 0, qsgmii)
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SWITCH_PORT_SDS(49, 52, 12, 1, qsgmii)
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SWITCH_PORT_SDS(50, 49, 12, 2, qsgmii)
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SWITCH_PORT_SDS(51, 51, 12, 3, qsgmii)
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};
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};
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&port48 {
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nvmem-cells = <&macaddr_factory 51>;
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nvmem-cell-names = "mac-address";
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};
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&port49 {
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nvmem-cells = <&macaddr_factory 53>;
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nvmem-cell-names = "mac-address";
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};
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&port50 {
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nvmem-cells = <&macaddr_factory 50>;
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nvmem-cell-names = "mac-address";
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};
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&port51 {
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nvmem-cells = <&macaddr_factory 52>;
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nvmem-cell-names = "mac-address";
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};
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