43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
164 lines
3.7 KiB
Plaintext
164 lines
3.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "rtl838x.dtsi"
|
|
#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
|
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
/ {
|
|
compatible = "panasonic,m16eg-pn28160k", "realtek,rtl8382-soc";
|
|
model = "Panasonic Switch-M16eG PN28160K";
|
|
|
|
aliases {
|
|
led-boot = &led_status_eco_green;
|
|
led-failsafe = &led_status_eco_amber;
|
|
led-running = &led_status_eco_green;
|
|
led-upgrade = &led_status_eco_green;
|
|
};
|
|
|
|
/*
|
|
* sfp0/1 are "combo" port with each TP port (23/24), and they are
|
|
* connected to the RTL8218FB. Currently, there is no support for
|
|
* the chip and only TP ports work by the RTL8218D support.
|
|
*/
|
|
sfp0: sfp-p23 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c0>;
|
|
tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
|
|
tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
|
los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sfp1: sfp-p24 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c1>;
|
|
tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
|
tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
|
los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
&leds {
|
|
led_status_eco_amber: led-5 {
|
|
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
|
color = <LED_COLOR_ID_AMBER>;
|
|
function = LED_FUNCTION_STATUS;
|
|
function-enumerator = <1>;
|
|
};
|
|
|
|
led_status_eco_green: led-6 {
|
|
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
|
color = <LED_COLOR_ID_GREEN>;
|
|
function = LED_FUNCTION_STATUS;
|
|
function-enumerator = <2>;
|
|
};
|
|
};
|
|
|
|
&i2c_gpio_0 {
|
|
scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
};
|
|
|
|
&i2c_gpio_1 {
|
|
scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
};
|
|
|
|
&gpio2 {
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&gpio0>;
|
|
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
|
|
|
|
/*
|
|
* GPIO12 (IO1_4): RTL8218FB
|
|
*
|
|
* This GPIO pin should be specified as "reset-gpio" in mdio node, but
|
|
* RTL8218FB phy won't be configured on RTL8218D support in the current
|
|
* phy driver. So, ethernet ports on the phy will be broken after hard-
|
|
* resetting.
|
|
* (RTL8218FB phy will be detected as RTL8218D by the phy driver)
|
|
* At the moment, configure this GPIO pin as gpio-hog to avoid breaking
|
|
* by resetting.
|
|
*/
|
|
ext_switch_reset {
|
|
gpio-hog;
|
|
gpios = <12 GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
line-name = "ext-switch-reset";
|
|
};
|
|
};
|
|
|
|
&i2c_switch {
|
|
i2c0: i2c@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
};
|
|
|
|
i2c1: i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
&mdio_bus0 {
|
|
PHY_C22(8, 8)
|
|
PHY_C22(9, 9)
|
|
PHY_C22(10, 10)
|
|
PHY_C22(11, 11)
|
|
PHY_C22(12, 12)
|
|
PHY_C22(13, 13)
|
|
PHY_C22(14, 14)
|
|
PHY_C22(15, 15)
|
|
|
|
/* RTL8218FB */
|
|
PHY_C22(16, 16)
|
|
PHY_C22(17, 17)
|
|
PHY_C22(18, 18)
|
|
PHY_C22(19, 19)
|
|
PHY_C22(20, 20)
|
|
PHY_C22(21, 21)
|
|
PHY_C22(22, 22)
|
|
PHY_C22(23, 23)
|
|
};
|
|
|
|
&switch0 {
|
|
ethernet-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
SWITCH_PORT(8, 1, internal)
|
|
SWITCH_PORT(9, 2, internal)
|
|
SWITCH_PORT(10, 3, internal)
|
|
SWITCH_PORT(11, 4, internal)
|
|
SWITCH_PORT(12, 5, internal)
|
|
SWITCH_PORT(13, 6, internal)
|
|
SWITCH_PORT(14, 7, internal)
|
|
SWITCH_PORT(15, 8, internal)
|
|
|
|
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
|
|
SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
|
|
SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
|
|
SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
|
|
SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
|
|
SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
|
|
SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
|
|
SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
|
|
|
|
port@28 {
|
|
ethernet = <ðernet0>;
|
|
reg = <28>;
|
|
phy-mode = "internal";
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
};
|
|
};
|