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openwrt/target/linux/realtek/dts/rtl9303_xikestor_sks7300-4x4t.dts
Jonas Jelonek 43562f97e7
realtek: dts: add link index cell to pcs-handle phandles
A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.

The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.

Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.

No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.

Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-05-31 12:52:40 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "rtl930x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "xikestor,sks7300-4x4t", "realtek,rtl9303-soc";
model = "XikeStor SKS7300-4X4T";
aliases {
label-mac-device = &ethernet0;
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>, /* first 256 MiB */
<0x20000000 0x10000000>; /* remaining 256 MiB */
};
chosen {
stdout-path = "serial0:115200n8";
/* Silencing the kernel is required since otherwise the watchdog
would time out! */
bootargs = "quiet";
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
hw_algo = "toggle";
hw_margin_ms = <1200>;
always-running;
};
keys {
compatible = "gpio-keys";
button-reset {
label = "reset";
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_led_sync>, <&pinmux_disable_sys_led>;
led_sys: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
led_set {
compatible = "realtek,rtl9300-leds";
active-low;
/* [Amber] [Green] */
led_set0 = <(RTL93XX_LED_SET_5G | RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G |
RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
};
i2c_gpio {
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
i2c-gpio,delay-us = <2>;
scl-gpios = <&gpio0 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio0 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
temperature_sensor: temperature-sensor@48 {
compatible = "national,lm75";
reg = <0x48>;
#thermal-sensor-cells = <0>;
};
};
sfp0: sfp-p1 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
los-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <1500>;
#thermal-sensor-cells = <0>;
};
sfp1: sfp-p2 {
compatible = "sff,sfp";
i2c-bus = <&i2c3>;
los-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <1500>;
#thermal-sensor-cells = <0>;
};
sfp2: sfp-p3 {
compatible = "sff,sfp";
i2c-bus = <&i2c4>;
los-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <1500>;
#thermal-sensor-cells = <0>;
};
sfp3: sfp-p4 {
compatible = "sff,sfp";
i2c-bus = <&i2c6>;
los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <1500>;
#thermal-sensor-cells = <0>;
};
};
&i2c_mst1 {
status = "okay";
i2c2: i2c@2 {
reg = <2>;
};
i2c3: i2c@3 {
reg = <3>;
};
i2c4: i2c@4 {
reg = <4>;
};
i2c6: i2c@6 {
reg = <6>;
};
};
&mdio_aux {
status = "okay";
gpio1: gpio@0 {
compatible = "realtek,rtl8231";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio1 0 0 37>;
led-controller {
compatible = "realtek,rtl8231-leds";
status = "disabled";
};
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0xa0000>;
read-only;
};
partition@a0000 {
label = "u-boot-env";
reg = <0xa0000 0x10000>;
nvmem-layout {
compatible = "u-boot,env";
macaddr_ubootenv_ethaddr: ethaddr {
#nvmem-cell-cells = <1>;
};
};
};
partition@b0000 {
label = "reserve";
reg = <0xb0000 0x80000>;
read-only;
};
partition@130000 {
label = "config";
reg = <0x130000 0x350000>;
read-only;
};
partition@480000 {
label = "firmware";
reg = <0x480000 0x1b80000>;
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x800000>;
};
partition@800000 {
label = "rootfs";
reg = <0x800000 0x1380000>;
};
};
};
};
};
&ethernet0 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
};
&mdio_bus0 {
PHY_C45(24, 0)
};
&mdio_bus1 {
PHY_C45(25, 0)
};
&mdio_bus2 {
PHY_C45(26, 0)
PHY_C45(27, 1)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SFP(0, 1, 2, 0, 0)
SWITCH_PORT_SFP(8, 2, 3, 0, 1)
SWITCH_PORT_SFP(16, 3, 4, 0, 2)
SWITCH_PORT_SFP(20, 4, 5, 0, 3)
SWITCH_PORT_SDS(24, 8, 6, 0, usxgmii)
SWITCH_PORT_SDS(25, 7, 7, 0, usxgmii)
SWITCH_PORT_SDS(26, 6, 8, 0, usxgmii)
SWITCH_PORT_SDS(27, 5, 9, 0, usxgmii)
port@28 {
ethernet = <&ethernet0>;
reg = <28>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&thermal_zones {
sys-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&temperature_sensor>;
trips {
sys-crit {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};