catspeed-cc/openwrt
1
1
Fork 0
Code
43562f97e7
openwrt/target/linux/realtek/dts/rtl9302_xikestor_sks8300-12e2t2x.dts
Jonas Jelonek 43562f97e7
realtek: dts: add link index cell to pcs-handle phandles 
A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.

The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.

Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.

No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.

Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-05-31 12:52:40 +02:00

236 lines
4.9 KiB
Plaintext
Raw Blame History

// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
#include "rtl930x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "xikestor,sks8300-12e2t2x", "realtek,rtl9302-soc";
model = "XikeStor SKS8300-12E2T2X";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x10000000>, /* first 256 MiB */
<0x20000000 0x10000000>; /* remaining 256 MiB */
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
/* The following sets up the GPIO pin for the HC595 shift registers.
Since there are no LED nodes defined for this switch, do the setup
in the GPIO keys driver. */
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_led_sync>;
button-reset {
label = "reset";
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
led_set {
compatible = "realtek,rtl9300-leds";
active-low;
/*
* 2,5G Ports LED0 (orange): 10M/100M/1G/LINK/ACT
* 2,5G Ports LED1 (green): 2.5G/LINK/ACT
*/
led_set0 = <(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
/*
* 10G Ports LED0 (orange): 10M/100M/1G/2.5G/5G/LINK/ACT
* 10G Ports LED1 (green): 10G/LINK/ACT
*/
led_set1 = <(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_5G |
RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
};
sfp0: sfp-p15 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp0>;
maximum-power-milliwatt = <1500>;
mod-def0-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
los-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
};
sfp1: sfp-p16 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
maximum-power-milliwatt = <1500>;
mod-def0-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
los-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
tx-disable-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
};
aliases {
label-mac-device = &ethernet0;
};
};
&i2c_mst1 {
status = "okay";
i2c_sfp0: i2c@0 {
reg = <0>;
};
i2c_sfp1: i2c@1 {
reg = <1>;
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x1c0000>;
read-only;
};
partition@1c0000 {
label = "u-boot-env";
reg = <0x1c0000 0x10000>;
};
partition@1d0000 {
label = "sysinfo";
reg = <0x1d0000 0x10000>;
read-only;
};
partition@1e0000 {
label = "factory";
reg = <0x1e0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
factory_macaddr: macaddr@80 {
reg = <0x80 0x6>;
};
};
};
partition@1f0000 {
label = "sysdata";
reg = <0x1f0000 0x10000>;
};
partition@200000 {
label = "jffs2_filesystem";
reg = <0x200000 0xa00000>;
};
partition@c00000 {
compatible = "openwrt,uimage", "denx,uimage";
label = "firmware";
reg = <0xc00000 0x1400000>;
openwrt,ih-magic = <0x93000000>;
openwrt,offset = <0x10>;
};
};
};
};
&ethernet0 {
nvmem-cells = <&factory_macaddr>;
nvmem-cell-names = "mac-address";
};
&mdio_bus0 {
PHY_C45(0, 0)
PHY_C45(1, 1)
PHY_C45(2, 2)
PHY_C45(3, 3)
};
&mdio_bus1 {
PHY_C45(8, 0)
PHY_C45(9, 1)
PHY_C45(10, 2)
PHY_C45(11, 3)
};
&mdio_bus2 {
PHY_C45(16, 0)
PHY_C45(17, 1)
PHY_C45(18, 2)
PHY_C45(19, 3)
};
&mdio_bus3 {
PHY_C45(24, 0)
PHY_C45(25, 1)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_LED(0, 2, 2, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(1, 1, 2, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(2, 4, 2, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(3, 3, 2, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(8, 6, 3, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(9, 5, 3, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(10, 8, 3, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(11, 7, 3, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(16, 10, 4, 0, 0, 10g-qxgmii)
SWITCH_PORT_LED(17, 9, 4, 1, 0, 10g-qxgmii)
SWITCH_PORT_LED(18, 12, 4, 2, 0, 10g-qxgmii)
SWITCH_PORT_LED(19, 11, 4, 3, 0, 10g-qxgmii)
SWITCH_PORT_LED(24, 13, 6, 0, 1, usxgmii)
SWITCH_PORT_LED(25, 14, 7, 0, 1, usxgmii)
SWITCH_PORT_SFP(26, 15, 8, 1, 0)
SWITCH_PORT_SFP(27, 16, 9, 1, 1)
port@28 {
reg = <28>;
ethernet = <&ethernet0>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&thermal_zones {
sfp-thermal {
polling-delay-passive = <10000>;
polling-delay = <10000>;
thermal-sensors = <&sfp0>, <&sfp1>;
trips {
sfp-crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
View Git Blame Copy Permalink