43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
89 lines
1.4 KiB
Plaintext
89 lines
1.4 KiB
Plaintext
/dts-v1/;
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#include "rtl839x_zyxel_gs1920-24hp-common.dtsi"
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/ {
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compatible = "zyxel,gs1920-24hp-v1", "realtek,rtl8392-soc";
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model = "Zyxel GS1920-24HPv1";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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chosen {
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stdout-path = "serial0:9600n8";
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};
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leds {
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alarm {
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gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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function = LED_FUNCTION_FAULT;
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color = <LED_COLOR_ID_RED>;
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};
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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mode {
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label = "reset";
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gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&i2c4 {
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adt7468: adt7468@2e {
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compatible = "adi,adt7468";
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reg = <0x2e>;
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};
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};
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&flash_partitions {
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partition@20000 {
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label = "reserved";
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reg = <0x20000 0x90000>;
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read-only;
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};
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partition@b0000 {
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reg = <0xb0000 0xf50000>;
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label = "factory";
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "loader";
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reg = <0x0 0x10000>;
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};
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partition@10000 {
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label = "firmware";
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reg = <0x10000 0xf40000>;
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compatible = "openwrt,uimage", "denx,uimage";
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};
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};
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};
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&mdio_bus1 {
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/* External phy RTL8214FC #1 */
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PHY_C22_SFP(48, 24, 0)
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PHY_C22_SFP(49, 25, 1)
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PHY_C22_SFP(50, 26, 2)
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PHY_C22_SFP(51, 27, 3)
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};
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&switch0 {
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ethernet-ports {
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SWITCH_PORT_SDS(48, 25, 12, 0, qsgmii)
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SWITCH_PORT_SDS(49, 26, 12, 1, qsgmii)
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SWITCH_PORT_SDS(50, 27, 12, 2, qsgmii)
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SWITCH_PORT_SDS(51, 28, 12, 3, qsgmii)
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};
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};
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