A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.
The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.
Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.
No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.
Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
The RTL839x actually has two mdio busses.
- mdio bus 0 serves ports 0..23
- mdio bus 1 serves ports 24..51
This is baked into hardware and cannot be changed during mdio driver
setup with any register write. With the recent changes the driver
handles ports, phys and busses in a more logical way. So a port X
is assigned to a bus Y and a phy Z (on that bus). This gives a
mapping like
- port 16 <=> bus 0, address 16
- port 32 <=> bus 1, address 8
This unique assignment is used in the mdio driver as follows:
- Request to read bus 1, address 8
- Lookup corresponding port = 32
- Read from port 32
Looking at RTL839x it becomes clear that bus/phy => port lookup can
be achieved in multiple different ways. The simple reason is, that
for this device the driver cannot setup the smi topology. It is
baked into the hardware. So adding a "virtual" second bus does not
change the hardware access but allows to keep phy addresses below 32.
Making an example
mdio_bus0 {
PHY_C22(40, 40)
}
resolves to port 40. But the same can be achieved with
mdio_bus1 {
PHY_C22(40, 16)
}
In the first case the kernel sees bus/phy = 0/40 and in the second
case it sees bus/phy = 1/16. Both result in the access to the same
phy device on hardware port 40.
Use this analogy for RTL839x devices to match the real hardware
topology. For this change the existing dts and
- activate mdio bus 1 in rtl839x.dtsi
- rearrange devices with ports 24..51 to make use of bus 1
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23186
Signed-off-by: Robert Marko <robimarko@gmail.com>
Several EXTERNAL macros have been removed in the past. There is
no need to distinguish if a phy is built into the SoC or is
attached externally.
Do the same for EXTERNAL_SFP_PHY_FULL. This macro denotes a phy
that has a SFP port attached to it. This is usually RTL8214FC
based. To be consistent with other macros name it PHY_C22_SFP.
While we are here make use of the new port/phy notation.
So PHY_C22_SFP(p, n, s) gives
- p: the overall port number
- n: the phy address on the current bus
- s: the sfp identifier
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/23036
Signed-off-by: Robert Marko <robimarko@gmail.com>
In most drivers upstream use "ethernet-ports" instead of "ports"
in dts. Especially the upstream rtl9300 mdio driver uses this to
lookup the port/phy mapping. Do the same downstream. There is no
need to adapt the dsa driver because it scans the dts via
for_each_node_by_name(dn, "port").
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22149
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Move common parts shared with GS1920-24HPv2 from v1's DTS and image
definition into a common DTSI and device definition to prepare adding
support for GS1920-24HPv2.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21944
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
For the GS1920 the build system throws errors like
../dts/rtl8392_zyxel_gs1920-24hp-v1.dts:256.19-29:
Warning (reg_format): /switch@1b000000/ports/port@0:reg:
property has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
The dts misses the address and size properties for the
ports section. Fix that.
Fixes: 2a55846 ("realtek: add support for ZyXEL GS1920-24HPv1")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21534
Signed-off-by: Robert Marko <robimarko@gmail.com>
The GS1920-24HPv1 is a switch with 24 copper ports and 4 combo SFP/copper
ports and PoE on the first 24 ports.
Specifications:
---------------
* SoC: Realtek RTL8292M
* Flash: 16 MiB SPI flash
* RAM: 128 MiB
* Ethernet: 24x 10/100/1000 Mbps
* Buttons: 1x "Reset" button
* UART: 1x serial header, standard DCE pinout (Tx = 2, Rx = 3, Gnd = 5);
9600 baud, 8n1, +- 5.6V logic levels
* SFP: 4 combo copper/SFP ports
* PoE: 24x
* Fans: ADT7468 fan controller
Works:
------
- (24) RJ-45 ethernet ports
- Switch functions
- Buttons
- LEDs (partial support, the wrong LEDs light up)
- Manual fan control
Not yet enabled:
----------------
- PoE (requires patches to realtek-poe to support i2c)
- Combo ports (link is up, but no data is transferred)
Fans:
-----
After boot, the fans are running in full speed mode. You can interact
with the fan controller at /sys/class/hwmon/
Installation:
-------------
This device uses ZyNOS instead of Linux, this makes installation a bit
more cumbersome. Serial console is required!
1. Set the switch to boot from the first image. This step is crucial,
it will fail to boot if this is not set properly.
2. Connect to the switch using serial and interrupt the boot process
to enter debug/recovery mode.
3. Load the OpenWrt initramfs image via XMODEM. You need to obtain an
unlock code, based on your MAC address, first. See the excellent write
up at https://www.ixo.de/info/zyxel_uclinux/ for details. Replace
unlock_code in the commands below by the code obtained.
After running ATBA5, the terminal needs to be closed and re-opened
with 115200 baud. This speeds up the file transfer significantly!
The file length in bytes need to be given instead of file_length below.
You also need an XMODEM upload utility like "lrzsz-sx -X" to transfer
the file. Start the XMODEM upload after running the ATUPxxxx command:
> ATEN1,unlock_code
> ATBA5
> ATUP80100000,file_length
> ATGO80100000
4. Wait for OpenWrt to boot. Once this is done, transfer the loader binary
and the sysupgrade image to "/tmp" using scp.
5. Install OpenWrt permanently by running the following two commands on
the switch (over SSH):
> mtd write /tmp/loader.bin loader
> mtd write /tmp/sysupgrade.bin firmware
6. Reboot the switch and enjoy OpenWrt.
NB: You do not need to touch the loader binary unless it's recommended.
The loader is not part of a regular sysupgrade file and will be left
untouched. The boot loader only checks if the loader is valid to be
able to boot.
Recovery/ Return to stock:
--------------------------
Just spam the "u" key during (or "z" for 9600 baud) during memory testing
to trigger a recovery XMODEM upload at 115200 baud. A standard OEM upgrade
image works properly.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/20439
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
