43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
152 lines
2.6 KiB
Plaintext
152 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
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model = "INABA Abaniact AML2-17GP";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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keys {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x10000>;
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read-only;
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};
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partition@90000 {
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label = "u-boot-env2";
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reg = <0x90000 0x10000>;
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};
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partition@a0000 {
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label = "jffs2_cfg";
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reg = <0xa0000 0x400000>;
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read-only;
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};
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partition@4a0000 {
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label = "jffs2_log";
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reg = <0x4a0000 0x100000>;
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read-only;
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};
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partition@5a0000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x5a0000 0xd30000>;
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openwrt,ih-magic = <0x83800000>;
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};
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partition@12d0000 {
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label = "runtime2";
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reg = <0x12d0000 0xd30000>;
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};
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};
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};
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};
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&mdio_bus0 {
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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PHY_C22(24, 24)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
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SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
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SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
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SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
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SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
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SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
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SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
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SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
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port@24 {
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reg = <24>;
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label = "wan";
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phy-handle = <&phy24>;
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phy-mode = "qsgmii";
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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