openwrt/target/linux/realtek/dts/rtl9302_plasmacloud_common.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later

#include "rtl930x.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>

/ {
	chosen {
		/* get active mtdparts from u-boot */
		/delete-property/ bootargs;
	};

	aliases {
		led-boot = &led_power;
		led-running = &led_power;
		led-failsafe = &led_power;
		led-upgrade = &led_power;
		label-mac-device = &ethernet0;
	};

	keys {
		compatible = "gpio-keys";

		mode {
			label = "reset";
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	i2c0: i2c-gpio0 {
		compatible = "i2c-gpio";
		#address-cells = <1>;
		#size-cells = <0>;

		sda-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
		scl-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;

		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
	};

	leds {
		compatible = "gpio-leds";

		pinctrl-names = "default";
		pinctrl-0 = <&pinmux_disable_sys_led>;

		led_power: led-0 {
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_POWER;
			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};

		led-1 {
			color = <LED_COLOR_ID_RED>;
			function = LED_FUNCTION_STATUS;
			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
	};

	led_set: led_set@0 {
		compatible = "realtek,rtl9300-leds";
		active-low;

		led_set0 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G |
			     RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G |
			     RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
			     RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0xe0000>;
				read-only;
			};

			partition@e0000 {
				label = "u-boot-env";
				reg = <0xe0000 0x10000>;

				nvmem-layout {
					compatible = "u-boot,env";

					macaddr_ubootenv_ethaddr: ethaddr {
						#nvmem-cell-cells = <1>;
					};
				};
			};

			partition@f0000 {
				label = "u-boot-env2";
				reg = <0xf0000 0x10000>;
			};

			partition@100000 {
				label = "firmware1";
				reg = <0x100000 0xf80000>;
				compatible = "openwrt,uimage", "denx,uimage";
				openwrt,ih-magic = <0x93000000>;
			};

			partition@1080000 {
				label = "firmware2";
				reg = <0x1080000 0xf80000>;
				compatible = "openwrt,uimage", "denx,uimage";
				openwrt,ih-magic = <0x93000000>;
			};
		};
	};
};

&ethernet0 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
	nvmem-cell-names = "mac-address";
};

&mdio_bus0 {
	PHY_C45_PAIR_ORDER(0, 0, 0)
	PHY_C45_PAIR_ORDER(1, 1, 0)
	PHY_C45_PAIR_ORDER(2, 2, 1)
	PHY_C45_PAIR_ORDER(3, 3, 1)
	PHY_C45_PAIR_ORDER(8, 4, 0)
	PHY_C45_PAIR_ORDER(9, 5, 0)
	PHY_C45_PAIR_ORDER(10, 6, 1)
	PHY_C45_PAIR_ORDER(11, 7, 1)
};

&switch0 {
	ethernet-ports {
		#address-cells = <1>;
		#size-cells = <0>;

		SWITCH_PORT_SDS(0, 1, 2, 0, 10g-qxgmii)
		SWITCH_PORT_SDS(1, 2, 2, 1, 10g-qxgmii)
		SWITCH_PORT_SDS(2, 3, 2, 2, 10g-qxgmii)
		SWITCH_PORT_SDS(3, 4, 2, 3, 10g-qxgmii)
		SWITCH_PORT_SDS(8, 5, 3, 0, 10g-qxgmii)
		SWITCH_PORT_SDS(9, 6, 3, 1, 10g-qxgmii)
		SWITCH_PORT_SDS(10, 7, 3, 2, 10g-qxgmii)
		SWITCH_PORT_SDS(11, 8, 3, 3, 10g-qxgmii)

		/* CPU-port */
		port@28 {
			ethernet = <&ethernet0>;
			reg = <28>;
			phy-mode = "internal";
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

&port0 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 1>;
	nvmem-cell-names = "mac-address";
};

&port1 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 2>;
	nvmem-cell-names = "mac-address";
};

&port2 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 3>;
	nvmem-cell-names = "mac-address";
};

&port3 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 4>;
	nvmem-cell-names = "mac-address";
};

&port8 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 5>;
	nvmem-cell-names = "mac-address";
};

&port9 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 6>;
	nvmem-cell-names = "mac-address";
};

&port10 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 7>;
	nvmem-cell-names = "mac-address";
};

&port11 {
	nvmem-cells = <&macaddr_ubootenv_ethaddr 8>;
	nvmem-cell-names = "mac-address";
};

&gpio0 {
	/*
	 * GPIO 6 is the global reset shared by (logical) PHYs 0-3 on MDIO bus0.
	 * It is intentionally not declared as reset-gpios on any bus: the MDIO
	 * driver / phylink only support a single reset GPIO per bus, not two
	 * (or more). And a GPIO can only be used as reset-gpio on a single PHY.
	 * Attaching it to a single PHY would still reset the other PHYs on
	 * the same chip as a side effect, leaving their software state out of
	 * sync with the hardware and likely breaking them.
	 */
	phy_reset1 {
		gpio-hog;
		gpios = <6 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "phy-reset-lan1-4";
	};

	/*
	 * GPIO 10 is the global reset shared by (logical) PHYs 8-11 on MDIO
	 * bus0. It is intentionally not declared as reset-gpios on any bus:
	 * the MDIO driver / phylink only support a single reset GPIO per bus,
	 * not two (or more). And a GPIO can only be used as reset-gpio on a
	 * single PHY. Attaching it to a single PHY would still reset the other
	 * PHYs on the same chip as a side effect, leaving their software state
	 * out of sync with the hardware and likely breaking them.
	 */
	phy_reset2 {
		gpio-hog;
		gpios = <10 GPIO_ACTIVE_LOW>;
		output-low;
		line-name = "phy-reset-lan5-8";
	};
};