43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
131 lines
2.6 KiB
Plaintext
131 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "rtl838x.dtsi"
|
|
#include "rtl83xx_d-link_dgs-1210_common.dtsi"
|
|
#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
|
|
|
|
/ {
|
|
compatible = "d-link,dgs-1210-10p", "realtek,rtl838x-soc";
|
|
model = "D-Link DGS-1210-10P";
|
|
|
|
/* i2c of the left SFP cage: port 9 */
|
|
i2c0: i2c-gpio-0 {
|
|
compatible = "i2c-gpio";
|
|
sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
i2c-gpio,delay-us = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
sfp0: sfp-p9 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c0>;
|
|
los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
|
tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
/* i2c of the right SFP cage: port 10 */
|
|
i2c1: i2c-gpio-1 {
|
|
compatible = "i2c-gpio";
|
|
sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
i2c-gpio,delay-us = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
sfp1: sfp-p10 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c1>;
|
|
los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
|
tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
leds {
|
|
link_act {
|
|
label = "green:link_act";
|
|
gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
poe {
|
|
label = "green:poe";
|
|
gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
poe_max {
|
|
label = "yellow:poe_max";
|
|
gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&keys {
|
|
mode {
|
|
label = "mode";
|
|
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_LIGHTS_TOGGLE>;
|
|
};
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mdio_bus0 {
|
|
PHY_C22(8, 8)
|
|
PHY_C22(9, 9)
|
|
PHY_C22(10, 10)
|
|
PHY_C22(11, 11)
|
|
PHY_C22(12, 12)
|
|
PHY_C22(13, 13)
|
|
PHY_C22(14, 14)
|
|
PHY_C22(15, 15)
|
|
};
|
|
|
|
&switch0 {
|
|
ethernet-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
SWITCH_PORT(8, 1, internal)
|
|
SWITCH_PORT(9, 2, internal)
|
|
SWITCH_PORT(10, 3, internal)
|
|
SWITCH_PORT(11, 4, internal)
|
|
SWITCH_PORT(12, 5, internal)
|
|
SWITCH_PORT(13, 6, internal)
|
|
SWITCH_PORT(14, 7, internal)
|
|
SWITCH_PORT(15, 8, internal)
|
|
|
|
port@24 {
|
|
reg = <24>;
|
|
label = "lan9";
|
|
pcs-handle = <&serdes4 0>;
|
|
phy-mode = "1000base-x";
|
|
managed = "in-band-status";
|
|
sfp = <&sfp0>;
|
|
};
|
|
|
|
port@26 {
|
|
reg = <26>;
|
|
label = "lan10";
|
|
pcs-handle = <&serdes5 0>;
|
|
phy-mode = "1000base-x";
|
|
managed = "in-band-status";
|
|
sfp = <&sfp1>;
|
|
};
|
|
|
|
port@28 {
|
|
ethernet = <ðernet0>;
|
|
reg = <28>;
|
|
phy-mode = "internal";
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
};
|
|
};
|