43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
418 lines
8.3 KiB
Plaintext
418 lines
8.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl839x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "tplink,sg2452p-v4", "realtek,rtl8393-soc";
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model = "TP-Link SG2452P v4";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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label-mac-device = ðernet0;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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speed {
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label = "speed";
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gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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};
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gpio_fan_sys {
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compatible = "gpio-fan";
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alarm-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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};
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gpio_fan_psu_1 {
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pinctrl-names = "default";
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pinctrl-0 = <&disable_jtag>;
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compatible = "gpio-fan";
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alarm-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
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/* the actual speeds (rpm) are unknown, just use dummy values */
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gpio-fan,speed-map = <1 0>, <2 1>;
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#cooling-cells = <2>;
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};
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gpio_fan_psu_2 {
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/* This fan runs in parallel to PSU1 fan, but has a separate
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* alarm GPIO. This is not (yet) supported by the gpio-fan driver,
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* so a separate instance is added
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*/
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compatible = "gpio-fan";
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alarm-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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leds {
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pinctrl-names = "default";
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compatible = "gpio-leds";
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led-0 {
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gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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};
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led-1 {
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gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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};
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led_sys: led-2 {
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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led-3 {
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gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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led-4 {
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gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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function = "fault-fan";
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};
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led-5 {
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gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = "alarm-poe";
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};
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};
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i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* LAN9 - LAN12 */
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tps23861@5 {
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compatible = "ti,tps23861";
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reg = <0x05>;
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};
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/* LAN17 - LAN20 */
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tps23861@6 {
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compatible = "ti,tps23861";
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reg = <0x06>;
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};
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/* LAN45 - LAN48 */
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tps23861@9 {
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compatible = "ti,tps23861";
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reg = <0x09>;
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};
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/* LAN37 - LAN40 */
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tps23861@a {
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compatible = "ti,tps23861";
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reg = <0x0a>;
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};
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/* LAN1 - LAN4 */
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tps23861@14 {
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compatible = "ti,tps23861";
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reg = <0x14>;
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};
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/* LAN25 - LAN28 */
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tps23861@24 {
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compatible = "ti,tps23861";
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reg = <0x24>;
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};
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/* LAN33 - LAN 36 */
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tps23861@25 {
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compatible = "ti,tps23861";
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reg = <0x25>;
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};
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/* LAN41 - LAN44 */
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tps23861@26 {
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compatible = "ti,tps23861";
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reg = <0x26>;
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};
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/* LAN13 - LAN16 */
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tps23861@29 {
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compatible = "ti,tps23861";
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reg = <0x29>;
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};
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/* LAN29 - LAN32 */
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tps23861@2c {
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compatible = "ti,tps23861";
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reg = <0x2c>;
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};
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/* LAN5 - LAN8 */
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tps23861@48 {
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compatible = "ti,tps23861";
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reg = <0x48>;
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};
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/* LAN21 - LAN24 */
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tps23861@49 {
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compatible = "ti,tps23861";
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reg = <0x49>;
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};
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
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};
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};
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&gpio0 {
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poe-enable {
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gpio-hog;
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gpios = <23 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-enable";
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0xe0000>;
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read-only;
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};
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partition@e0000 {
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label = "u-boot-env";
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reg = <0xe0000 0x20000>;
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};
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/* We use the "sys", "usrimg1" and "usrimg2" partitions
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* as firmware since the kernel needs to be in "sys", but the
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* partition is too small to hold the "rootfs" as well.
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* The original partition map contains:
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*
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* partition@100000 {
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* label = "sys";
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* reg = <0x100000 0x600000>;
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* };
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* partition@700000 {
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* label = "usrimg1";
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* reg = <0x700000 0xa00000>;
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* };
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* partition@1100000 {
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* label = "usrimg2";
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* reg = <0x1100000 0xa00000>;
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* };
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*/
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partition@100000 {
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label = "firmware";
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reg = <0x100000 0x1a00000>;
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};
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partition@1b00000 {
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label = "usrappfs";
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reg = <0x1b00000 0x400000>;
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};
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partition@1f00000 {
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label = "para";
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reg = <0x1f00000 0x100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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factory_macaddr: macaddr@fdff4 {
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reg = <0xfdff4 0x6>;
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};
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};
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&factory_macaddr>;
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nvmem-cell-names = "mac-address";
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};
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&mdio_bus0 {
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/* External phy RTL8218B #1 */
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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/* External phy RTL8218B #2 */
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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/* External phy RTL8218B #3 */
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&mdio_bus1 {
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/* External phy RTL8218B #4 */
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PHY_C22(24, 0)
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PHY_C22(25, 1)
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PHY_C22(26, 2)
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PHY_C22(27, 3)
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PHY_C22(28, 4)
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PHY_C22(29, 5)
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PHY_C22(30, 6)
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PHY_C22(31, 7)
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/* External phy RTL8218B #5 */
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PHY_C22(32, 8)
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PHY_C22(33, 9)
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PHY_C22(34, 10)
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PHY_C22(35, 11)
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PHY_C22(36, 12)
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PHY_C22(37, 13)
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PHY_C22(38, 14)
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PHY_C22(39, 15)
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/* External phy RTL8218B #6 */
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PHY_C22(40, 16)
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PHY_C22(41, 17)
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PHY_C22(42, 18)
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PHY_C22(43, 19)
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PHY_C22(44, 20)
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PHY_C22(45, 21)
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PHY_C22(46, 22)
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PHY_C22(47, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
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SWITCH_PORT_SDS(8, 9, 2, 0, qsgmii)
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SWITCH_PORT_SDS(9, 10, 2, 1, qsgmii)
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SWITCH_PORT_SDS(10, 11, 2, 2, qsgmii)
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SWITCH_PORT_SDS(11, 12, 2, 3, qsgmii)
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SWITCH_PORT_SDS(12, 13, 3, 0, qsgmii)
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SWITCH_PORT_SDS(13, 14, 3, 1, qsgmii)
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SWITCH_PORT_SDS(14, 15, 3, 2, qsgmii)
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SWITCH_PORT_SDS(15, 16, 3, 3, qsgmii)
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SWITCH_PORT_SDS(16, 17, 4, 0, qsgmii)
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SWITCH_PORT_SDS(17, 18, 4, 1, qsgmii)
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SWITCH_PORT_SDS(18, 19, 4, 2, qsgmii)
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SWITCH_PORT_SDS(19, 20, 4, 3, qsgmii)
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SWITCH_PORT_SDS(20, 21, 5, 0, qsgmii)
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SWITCH_PORT_SDS(21, 22, 5, 1, qsgmii)
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SWITCH_PORT_SDS(22, 23, 5, 2, qsgmii)
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SWITCH_PORT_SDS(23, 24, 5, 3, qsgmii)
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SWITCH_PORT_SDS(24, 25, 6, 0, qsgmii)
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SWITCH_PORT_SDS(25, 26, 6, 1, qsgmii)
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SWITCH_PORT_SDS(26, 27, 6, 2, qsgmii)
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SWITCH_PORT_SDS(27, 28, 6, 3, qsgmii)
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SWITCH_PORT_SDS(28, 29, 7, 0, qsgmii)
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SWITCH_PORT_SDS(29, 30, 7, 1, qsgmii)
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SWITCH_PORT_SDS(30, 31, 7, 2, qsgmii)
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SWITCH_PORT_SDS(31, 32, 7, 3, qsgmii)
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SWITCH_PORT_SDS(32, 33, 8, 0, qsgmii)
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SWITCH_PORT_SDS(33, 34, 8, 1, qsgmii)
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SWITCH_PORT_SDS(34, 35, 8, 2, qsgmii)
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SWITCH_PORT_SDS(35, 36, 8, 3, qsgmii)
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SWITCH_PORT_SDS(36, 37, 9, 0, qsgmii)
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SWITCH_PORT_SDS(37, 38, 9, 1, qsgmii)
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SWITCH_PORT_SDS(38, 39, 9, 2, qsgmii)
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SWITCH_PORT_SDS(39, 40, 9, 3, qsgmii)
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SWITCH_PORT_SDS(40, 41, 10, 0, qsgmii)
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SWITCH_PORT_SDS(41, 42, 10, 1, qsgmii)
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SWITCH_PORT_SDS(42, 43, 10, 2, qsgmii)
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SWITCH_PORT_SDS(43, 44, 10, 3, qsgmii)
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SWITCH_PORT_SDS(44, 45, 11, 0, qsgmii)
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SWITCH_PORT_SDS(45, 46, 11, 1, qsgmii)
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SWITCH_PORT_SDS(46, 47, 11, 2, qsgmii)
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SWITCH_PORT_SDS(47, 48, 11, 3, qsgmii)
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/* CPU-Port */
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port@52 {
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ethernet = <ðernet0>;
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reg = <52>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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