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openwrt/target/linux/realtek/dts/rtl9312_plasmacloud_common.dtsi
Jonas Jelonek 43562f97e7
realtek: dts: add link index cell to pcs-handle phandles 
A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.

The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.

Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.

No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.

Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-05-31 12:52:40 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "rtl931x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
/ {
chosen {
/* get active mtdparts from u-boot */
/delete-property/ bootargs;
};
aliases {
led-boot = &led_status;
led-running = &led_status;
led-failsafe = &led_status;
led-upgrade = &led_status;
label-mac-device = &ethernet0;
};
memory@0 {
reg = <0x00000000 0x10000000>, /* low mem 256 MiB */
<0x90000000 0x10000000>; /* high mem 256 MiB */
};
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <20>;
mode {
label = "reset";
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
sfp0: sfp-lan25 {
compatible = "sff,sfp";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_spi0>;
i2c-bus = <&i2c0>;
los-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 9 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
};
sfp1: sfp-lan26 {
compatible = "sff,sfp";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_spi0_cs0>,
<&pinmux_disable_spi0_cs1>;
i2c-bus = <&i2c1>;
los-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
};
sfp2: sfp-lan27 {
compatible = "sff,sfp";
i2c-bus = <&i2c2>;
los-gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>;
};
sfp3: sfp-lan28 {
compatible = "sff,sfp";
i2c-bus = <&i2c3>;
los-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_sys_led>;
led_status: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
};
led-1 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_ALARM;
gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
};
};
led_set@0 {
compatible = "realtek,rtl9300-leds";
active-low;
led_set0 = <(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M |
RTL93XX_LED_SET_10M | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)>;
led_set1 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)
(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK |
RTL93XX_LED_SET_ACT)>;
};
};
&i2c_mst1 {
status = "okay";
/* i2c of the SFP+ cage on port 24 */
i2c0: i2c@0 {
reg = <0>;
};
/* i2c of the SFP+ cage on port 25 */
i2c1: i2c@1 {
reg = <1>;
};
/* i2c of the SFP+ cage on port 26 */
i2c2: i2c@2 {
reg = <2>;
};
/* i2c of the SFP+ cage on port 27 */
i2c3: i2c@3 {
reg = <3>;
};
/* i2c of adt7476 hwmonitor */
i2c@4 {
reg = <4>;
adt7476@2e {
compatible = "adi,adt7476";
reg = <0x2e>;
};
};
};
&mdio_aux {
status = "okay";
gpio1: expander@24 {
compatible = "realtek,rtl8231";
reg = <24>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&gpio1 0 0 37>;
led-controller {
compatible = "realtek,rtl8231-leds";
status = "disabled";
};
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0xc0000>;
read-only;
};
partition@c0000 {
label = "u-boot-env";
reg = <0xc0000 0x10000>;
nvmem-layout {
compatible = "u-boot,env";
macaddr_ubootenv_ethaddr: ethaddr {
#nvmem-cell-cells = <1>;
};
};
};
partition@d0000 {
label = "u-boot-env2";
reg = <0xd0000 0x10000>;
};
partition@e0000 {
label = "reserved";
reg = <0xe0000 0x500000>;
};
partition@5e0000 {
label = "firmware1";
reg = <0x5e0000 0xd10000>;
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <0x93100000>;
};
partition@12f0000 {
label = "firmware2";
reg = <0x12f0000 0xd10000>;
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <0x93100000>;
};
};
};
};
&ethernet0 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
};
&mdio_ctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
<&pinmux_enable_mdc_mdio_1>;
};
&mdio_bus0 {
PHY_C45(0, 0)
PHY_C45(1, 1)
PHY_C45(4, 2)
PHY_C45(5, 3)
PHY_C45(8, 4)
PHY_C45(9, 5)
PHY_C45(12, 6)
PHY_C45(13, 7)
PHY_C45(16, 8)
PHY_C45(17, 9)
PHY_C45(20, 10)
PHY_C45(21, 11)
};
&mdio_bus1 {
PHY_C45(24, 12)
PHY_C45(25, 13)
PHY_C45(28, 14)
PHY_C45(29, 15)
PHY_C45(32, 16)
PHY_C45(33, 17)
PHY_C45(36, 18)
PHY_C45(37, 19)
PHY_C45(40, 20)
PHY_C45(41, 21)
PHY_C45(44, 22)
PHY_C45(45, 23)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
/* copper ethernet */
SWITCH_PORT_SDS(0, 1, 2, 0, 10g-qxgmii)
SWITCH_PORT_SDS(1, 2, 2, 1, 10g-qxgmii)
SWITCH_PORT_SDS(4, 3, 2, 2, 10g-qxgmii)
SWITCH_PORT_SDS(5, 4, 2, 3, 10g-qxgmii)
SWITCH_PORT_SDS(8, 5, 3, 0, 10g-qxgmii)
SWITCH_PORT_SDS(9, 6, 3, 1, 10g-qxgmii)
SWITCH_PORT_SDS(12, 7, 3, 2, 10g-qxgmii)
SWITCH_PORT_SDS(13, 8, 3, 3, 10g-qxgmii)
SWITCH_PORT_SDS(16, 9, 4, 0, 10g-qxgmii)
SWITCH_PORT_SDS(17, 10, 4, 1, 10g-qxgmii)
SWITCH_PORT_SDS(20, 11, 4, 2, 10g-qxgmii)
SWITCH_PORT_SDS(21, 12, 4, 3, 10g-qxgmii)
SWITCH_PORT_SDS(24, 13, 5, 0, 10g-qxgmii)
SWITCH_PORT_SDS(25, 14, 5, 1, 10g-qxgmii)
SWITCH_PORT_SDS(28, 15, 5, 2, 10g-qxgmii)
SWITCH_PORT_SDS(29, 16, 5, 3, 10g-qxgmii)
SWITCH_PORT_SDS(32, 17, 6, 0, 10g-qxgmii)
SWITCH_PORT_SDS(33, 18, 6, 1, 10g-qxgmii)
SWITCH_PORT_SDS(36, 19, 6, 2, 10g-qxgmii)
SWITCH_PORT_SDS(37, 20, 6, 3, 10g-qxgmii)
SWITCH_PORT_SDS(40, 21, 7, 0, 10g-qxgmii)
SWITCH_PORT_SDS(41, 22, 7, 1, 10g-qxgmii)
SWITCH_PORT_SDS(44, 23, 7, 2, 10g-qxgmii)
SWITCH_PORT_SDS(45, 24, 7, 3, 10g-qxgmii)
SWITCH_PORT_SFP(48, 25, 8, 1, 0)
SWITCH_PORT_SFP(50, 26, 9, 1, 1)
SWITCH_PORT_SFP(52, 27, 10, 1, 2)
SWITCH_PORT_SFP(53, 28, 11, 1, 3)
/* cpu */
port@56 {
ethernet = <&ethernet0>;
reg = <56>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&port0 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 1>;
nvmem-cell-names = "mac-address";
};
&port1 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 2>;
nvmem-cell-names = "mac-address";
};
&port4 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 3>;
nvmem-cell-names = "mac-address";
};
&port5 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 4>;
nvmem-cell-names = "mac-address";
};
&port8 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 5>;
nvmem-cell-names = "mac-address";
};
&port9 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 6>;
nvmem-cell-names = "mac-address";
};
&port12 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 7>;
nvmem-cell-names = "mac-address";
};
&port13 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 8>;
nvmem-cell-names = "mac-address";
};
&port16 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 9>;
nvmem-cell-names = "mac-address";
};
&port17 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 10>;
nvmem-cell-names = "mac-address";
};
&port20 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 11>;
nvmem-cell-names = "mac-address";
};
&port21 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 12>;
nvmem-cell-names = "mac-address";
};
&port24 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 13>;
nvmem-cell-names = "mac-address";
};
&port25 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 14>;
nvmem-cell-names = "mac-address";
};
&port28 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 15>;
nvmem-cell-names = "mac-address";
};
&port29 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 16>;
nvmem-cell-names = "mac-address";
};
&port32 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 17>;
nvmem-cell-names = "mac-address";
};
&port33 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 18>;
nvmem-cell-names = "mac-address";
};
&port36 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 19>;
nvmem-cell-names = "mac-address";
};
&port37 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 20>;
nvmem-cell-names = "mac-address";
};
&port40 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 21>;
nvmem-cell-names = "mac-address";
};
&port41 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 22>;
nvmem-cell-names = "mac-address";
};
&port44 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 23>;
nvmem-cell-names = "mac-address";
};
&port45 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 24>;
nvmem-cell-names = "mac-address";
};
&port48 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 25>;
nvmem-cell-names = "mac-address";
};
&port50 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 26>;
nvmem-cell-names = "mac-address";
};
&port52 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 27>;
nvmem-cell-names = "mac-address";
};
&port53 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 28>;
nvmem-cell-names = "mac-address";
};
&gpio0 {
/*
* GPIO 29 is the global reset shared by all PHYs across all MDIO busses.
* It is intentionally not declared as reset-gpios on any bus: the MDIO
* driver / phylink only support a reset GPIO per bus, not on the parent
* controller. Attaching it to a single bus would still reset the PHYs
* on the other busses as a side effect, leaving their software state
* out of sync with the hardware and likely breaking them.
*/
phy_reset {
gpio-hog;
gpios = <29 GPIO_ACTIVE_LOW>;
output-low;
line-name = "phy-reset";
};
};
&serdes8 { tx-polarity = <PHY_POL_INVERT>; };
&serdes9 { tx-polarity = <PHY_POL_INVERT>; };
&serdes10 { tx-polarity = <PHY_POL_INVERT>; };
&serdes11 { tx-polarity = <PHY_POL_INVERT>; };
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