43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
170 lines
3.2 KiB
Plaintext
170 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "tplink,t1600g-28ts-v3", "realtek,rtl838x-soc";
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model = "TP-Link T1600G-28TS v3";
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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label-mac-device = ðernet0;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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};
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leds {
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pinctrl-names = "default";
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compatible = "gpio-leds";
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led_sys: led-0 {
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0xe0000>;
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read-only;
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};
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partition@e0000 {
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label = "u-boot-env";
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reg = <0xe0000 0x20000>;
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};
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partition@100000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x100000 0x1a00000>;
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};
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partition@1b00000 {
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label = "usrappfs";
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reg = <0x1b00000 0x400000>;
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};
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partition@1f00000 {
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label = "para";
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reg = <0x1f00000 0x100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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factory_macaddr: macaddr@fdff4 {
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reg = <0xfdff4 0x6>;
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};
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};
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&factory_macaddr>;
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nvmem-cell-names = "mac-address";
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};
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&mdio_bus0 {
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_SDS(0, 1, 0, 0, qsgmii)
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SWITCH_PORT_SDS(1, 2, 0, 1, qsgmii)
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SWITCH_PORT_SDS(2, 3, 0, 2, qsgmii)
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SWITCH_PORT_SDS(3, 4, 0, 3, qsgmii)
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SWITCH_PORT_SDS(4, 5, 1, 0, qsgmii)
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SWITCH_PORT_SDS(5, 6, 1, 1, qsgmii)
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SWITCH_PORT_SDS(6, 7, 1, 2, qsgmii)
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SWITCH_PORT_SDS(7, 8, 1, 3, qsgmii)
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SWITCH_PORT(8, 9, internal)
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SWITCH_PORT(9, 10, internal)
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SWITCH_PORT(10, 11, internal)
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SWITCH_PORT(11, 12, internal)
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SWITCH_PORT(12, 13, internal)
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SWITCH_PORT(13, 14, internal)
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SWITCH_PORT(14, 15, internal)
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SWITCH_PORT(15, 16, internal)
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SWITCH_PORT_SDS(16, 17, 2, 0, qsgmii)
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SWITCH_PORT_SDS(17, 18, 2, 1, qsgmii)
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SWITCH_PORT_SDS(18, 19, 2, 2, qsgmii)
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SWITCH_PORT_SDS(19, 20, 2, 3, qsgmii)
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SWITCH_PORT_SDS(20, 21, 3, 0, qsgmii)
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SWITCH_PORT_SDS(21, 22, 3, 1, qsgmii)
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SWITCH_PORT_SDS(22, 23, 3, 2, qsgmii)
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SWITCH_PORT_SDS(23, 24, 3, 3, qsgmii)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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