43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
38 lines
772 B
Plaintext
38 lines
772 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
#include "rtl8380_zyxel_gs1900.dtsi"
|
|
#include "rtl8380_zyxel_gs1900_gpio.dtsi"
|
|
|
|
/ {
|
|
compatible = "zyxel,gs1900-16-a1", "realtek,rtl838x-soc";
|
|
model = "Zyxel GS1900-16 A1";
|
|
};
|
|
|
|
&mdio_bus0 {
|
|
PHY_C22(16, 16)
|
|
PHY_C22(17, 17)
|
|
PHY_C22(18, 18)
|
|
PHY_C22(19, 19)
|
|
PHY_C22(20, 20)
|
|
PHY_C22(21, 21)
|
|
PHY_C22(22, 22)
|
|
PHY_C22(23, 23)
|
|
};
|
|
|
|
&switch0 {
|
|
ethernet-ports {
|
|
SWITCH_PORT_SDS(16, 9, 2, 0, qsgmii)
|
|
SWITCH_PORT_SDS(17, 10, 2, 1, qsgmii)
|
|
SWITCH_PORT_SDS(18, 11, 2, 2, qsgmii)
|
|
SWITCH_PORT_SDS(19, 12, 2, 3, qsgmii)
|
|
SWITCH_PORT_SDS(20, 13, 3, 0, qsgmii)
|
|
SWITCH_PORT_SDS(21, 14, 3, 1, qsgmii)
|
|
SWITCH_PORT_SDS(22, 15, 3, 2, qsgmii)
|
|
SWITCH_PORT_SDS(23, 16, 3, 3, qsgmii)
|
|
};
|
|
};
|
|
|
|
&gpio1 {
|
|
/delete-node/ poe_enable;
|
|
};
|