A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.
The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.
Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.
No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.
Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
The Realtek target currently uses two phy macros to simplify the
device dts.
- EXTERNAL_PHY() to denote a phy attached to the SoC
- INTERNAL_PHY() to denote an internal PHY (inside the SoC)
There is no benefit doing this. The topology around a port/phy is
well defined by the port macros. They link port, phy, pcs and even
leds. The only consumer of the attribute "phy-is-integrated" is
inside the dsa driver and that is being refactored.
As a first step define a new more meaningful PHY_C22() macro that
describes a c22 capable phy. This does not need to care about the
external/internal relation. To make it even more useful for the
RTL93xx targets with multiple mdio busses give it two parameters
PHY_C22(port_number, bus_address) where
- port_number is the absolute overall unique phy number
- bus_address is the location of the phy on the bus
For RTL83xx these two parameters will usually be the same. Instead
of three steps (inventing the macro, converting the consumers and
removeing the old macor) do a one-step conversion for the existing
EXTERNAL_PHY() macro.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22698
Signed-off-by: Robert Marko <robimarko@gmail.com>
In most drivers upstream use "ethernet-ports" instead of "ports"
in dts. Especially the upstream rtl9300 mdio driver uses this to
lookup the port/phy mapping. Do the same downstream. There is no
need to adapt the dsa driver because it scans the dts via
for_each_node_by_name(dn, "port").
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22149
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
After having moved the configuration code and sequences from PHY and
DSA drivers to the PCS driver, add the hooks in PCS driver and remove
calls in PHY and DSA drivers to let PCS driver setup the SerDes
entirely on its own.
Also add pcs-handle to device tree definitions for most of the switch
ports because, due to the refactoring of the SerDes configuration, this
is needed now for all SerDes-attached ports.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20876
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Zyxel labels their switch revisions A1, B1, ... and not v1, v2, ...
Rename the devices as such in OpenWrt to match the labels. Of note:
the first (A1) revision is never labeled as such on the label, just
in the web UI. Provide compatibles for seamless sysupgrade.
For a recent overview of Zyxel GS1900 series revisions, see the
table linked in https://forum.openwrt.org/t//57875/3874.
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Link: https://github.com/openwrt/openwrt/pull/20118
Signed-off-by: Robert Marko <robimarko@gmail.com>
