43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
229 lines
4.4 KiB
Plaintext
229 lines
4.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
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/dts-v1/;
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#include "rtl931x.dtsi"
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#include "rtl93xx_linksys_lgs3xxc_nand_common.dtsi"
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "linksys,lgs352c", "realtek,rtl9311-soc";
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model = "Linksys LGS352C";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
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<0x90000000 0x10000000>; /* 256 MiB highmem */
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};
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};
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&i2c_mst1 {
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status = "okay";
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i2c2: i2c@2 {
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reg = <2>;
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lm63@4c {
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compatible = "national,lm63";
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reg = <0x4c>;
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};
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};
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i2c5: i2c@5 {
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reg = <5>;
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};
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i2c6: i2c@6 {
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reg = <6>;
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};
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i2c7: i2c@7 {
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reg = <7>;
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};
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i2c9: i2c@9 {
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reg = <9>;
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};
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};
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&sfp0 {
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i2c-bus = <&i2c5>;
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};
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&sfp1 {
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i2c-bus = <&i2c6>;
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};
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&sfp2 {
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i2c-bus = <&i2c7>;
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};
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&sfp3 {
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i2c-bus = <&i2c9>;
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};
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&mdio_aux {
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status = "okay";
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gpio1: expander@3 {
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compatible = "realtek,rtl8231";
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reg = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio1 0 0 37>;
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led-controller {
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compatible = "realtek,rtl8231-leds";
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status = "disabled";
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};
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};
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};
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&mdio_ctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
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<&pinmux_enable_mdc_mdio_1>;
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};
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&mdio_bus0 {
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&mdio_bus1 {
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PHY_C22(24, 0)
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PHY_C22(25, 1)
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PHY_C22(26, 2)
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PHY_C22(27, 3)
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PHY_C22(28, 4)
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PHY_C22(29, 5)
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PHY_C22(30, 6)
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PHY_C22(31, 7)
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PHY_C22(32, 8)
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PHY_C22(33, 9)
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PHY_C22(34, 10)
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PHY_C22(35, 11)
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PHY_C22(36, 12)
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PHY_C22(37, 13)
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PHY_C22(38, 14)
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PHY_C22(39, 15)
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PHY_C22(40, 16)
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PHY_C22(41, 17)
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PHY_C22(42, 18)
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PHY_C22(43, 19)
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PHY_C22(44, 20)
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PHY_C22(45, 21)
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PHY_C22(46, 22)
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PHY_C22(47, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_SDS(0, 1, 2, 0, usxgmii)
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SWITCH_PORT_SDS(1, 2, 2, 1, usxgmii)
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SWITCH_PORT_SDS(2, 3, 2, 2, usxgmii)
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SWITCH_PORT_SDS(3, 4, 2, 3, usxgmii)
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SWITCH_PORT_SDS(4, 5, 2, 4, usxgmii)
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SWITCH_PORT_SDS(5, 6, 2, 5, usxgmii)
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SWITCH_PORT_SDS(6, 7, 2, 6, usxgmii)
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SWITCH_PORT_SDS(7, 8, 2, 7, usxgmii)
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SWITCH_PORT_SDS(8, 9, 3, 0, usxgmii)
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SWITCH_PORT_SDS(9, 10, 3, 1, usxgmii)
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SWITCH_PORT_SDS(10, 11, 3, 2, usxgmii)
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SWITCH_PORT_SDS(11, 12, 3, 3, usxgmii)
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SWITCH_PORT_SDS(12, 13, 3, 4, usxgmii)
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SWITCH_PORT_SDS(13, 14, 3, 5, usxgmii)
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SWITCH_PORT_SDS(14, 15, 3, 6, usxgmii)
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SWITCH_PORT_SDS(15, 16, 3, 7, usxgmii)
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SWITCH_PORT_SDS(16, 17, 4, 0, usxgmii)
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SWITCH_PORT_SDS(17, 18, 4, 1, usxgmii)
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SWITCH_PORT_SDS(18, 19, 4, 2, usxgmii)
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SWITCH_PORT_SDS(19, 20, 4, 3, usxgmii)
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SWITCH_PORT_SDS(20, 21, 4, 4, usxgmii)
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SWITCH_PORT_SDS(21, 22, 4, 5, usxgmii)
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SWITCH_PORT_SDS(22, 23, 4, 6, usxgmii)
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SWITCH_PORT_SDS(23, 24, 4, 7, usxgmii)
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SWITCH_PORT_SDS(24, 25, 5, 0, usxgmii)
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SWITCH_PORT_SDS(25, 26, 5, 1, usxgmii)
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SWITCH_PORT_SDS(26, 27, 5, 2, usxgmii)
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SWITCH_PORT_SDS(27, 28, 5, 3, usxgmii)
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SWITCH_PORT_SDS(28, 29, 5, 4, usxgmii)
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SWITCH_PORT_SDS(29, 30, 5, 5, usxgmii)
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SWITCH_PORT_SDS(30, 31, 5, 6, usxgmii)
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SWITCH_PORT_SDS(31, 32, 5, 7, usxgmii)
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SWITCH_PORT_SDS(32, 33, 6, 0, usxgmii)
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SWITCH_PORT_SDS(33, 34, 6, 1, usxgmii)
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SWITCH_PORT_SDS(34, 35, 6, 2, usxgmii)
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SWITCH_PORT_SDS(35, 36, 6, 3, usxgmii)
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SWITCH_PORT_SDS(36, 37, 6, 4, usxgmii)
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SWITCH_PORT_SDS(37, 38, 6, 5, usxgmii)
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SWITCH_PORT_SDS(38, 39, 6, 6, usxgmii)
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SWITCH_PORT_SDS(39, 40, 6, 7, usxgmii)
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SWITCH_PORT_SDS(40, 41, 7, 0, usxgmii)
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SWITCH_PORT_SDS(41, 42, 7, 1, usxgmii)
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SWITCH_PORT_SDS(42, 43, 7, 2, usxgmii)
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SWITCH_PORT_SDS(43, 44, 7, 3, usxgmii)
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SWITCH_PORT_SDS(44, 45, 7, 4, usxgmii)
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SWITCH_PORT_SDS(45, 46, 7, 5, usxgmii)
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SWITCH_PORT_SDS(46, 47, 7, 6, usxgmii)
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SWITCH_PORT_SDS(47, 48, 7, 7, usxgmii)
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SWITCH_PORT_SFP(48, 49, 8, 0, 0)
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SWITCH_PORT_SFP(50, 50, 9, 0, 1)
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SWITCH_PORT_SFP(52, 51, 10, 0, 2)
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SWITCH_PORT_SFP(53, 52, 11, 0, 3)
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port@56 {
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ethernet = <ðernet0>;
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reg = <56>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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&serdes8 {
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes9 {
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes10 {
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tx-polarity = <PHY_POL_INVERT>;
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};
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&serdes11 {
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tx-polarity = <PHY_POL_INVERT>;
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};
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