43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
174 lines
3.3 KiB
Plaintext
174 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "hasivo,s1100w-8xgt-se", "realtek,rtl930x-soc";
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model = "Hasivo S1100W-8XGT-SE";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>, /* 256 MiB lowmem */
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<0x20000000 0x10000000>; /* 256 MiB highmem */
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};
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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};
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keys {
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compatible = "gpio-keys";
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button-reset {
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label = "reset";
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gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_sys: led-0 {
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gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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};
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led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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/*
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* LED set 0
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*
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* - LED[0](Amber): 5G/LINK/ACT
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* - LED[1](Green): 10G/LINK/ACT
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* - LED[2](Amber): 1G/100M/10M/LINK/ACT
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* - LED[3](Green): 2.5G/LINK/ACT
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*/
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led_set0 = <(RTL93XX_LED_SET_5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* stock is LOADER */
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partition@0 {
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label = "u-boot";
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reg = <0x0000000 0x00e0000>;
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read-only;
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};
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/* stock is BDINFO */
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partition@e0000 {
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label = "u-boot-env";
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reg = <0x00e0000 0x0010000>;
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};
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/* stock is SYSINFO */
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partition@f0000 {
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label = "u-boot-env2";
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reg = <0x00f0000 0x0010000>;
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read-only;
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};
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/* stock is JFFS2_CFG */
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partition@100000 {
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label = "jffs";
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reg = <0x0100000 0x0100000>;
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};
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/* stock is JFFS2_LOG */
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partition@200000 {
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label = "jffs2";
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reg = <0x0200000 0x0100000>;
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};
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/* stock is RUNTIME */
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partition@300000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x0300000 0x0c00000>;
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};
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/* stock is OEMINFO */
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partition@f00000 {
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label = "oeminfo";
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reg = <0x0f00000 0x0100000>;
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read-only;
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};
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};
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};
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};
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&mdio_bus0 {
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PHY_C45(0, 0)
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PHY_C45(8, 1)
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PHY_C45(16, 2)
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PHY_C45(20, 3)
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};
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&mdio_bus3 {
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PHY_C45(24, 16)
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PHY_C45(25, 17)
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PHY_C45(26, 18)
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PHY_C45(27, 19)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_LED(0, 1, 2, 0, 0, usxgmii)
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SWITCH_PORT_LED(8, 2, 3, 0, 0, usxgmii)
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SWITCH_PORT_LED(16, 3, 4, 0, 0, usxgmii)
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SWITCH_PORT_LED(20, 4, 5, 0, 0, usxgmii)
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SWITCH_PORT_LED(24, 5, 6, 0, 0, usxgmii)
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SWITCH_PORT_LED(25, 6, 7, 0, 0, usxgmii)
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SWITCH_PORT_LED(26, 7, 8, 0, 0, usxgmii)
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SWITCH_PORT_LED(27, 8, 9, 0, 0, usxgmii)
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/* Internal SoC */
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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