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openwrt/target/linux/realtek/dts/rtl9302_plasmacloud_mcx3.dts
Jonas Jelonek 43562f97e7
realtek: dts: add link index cell to pcs-handle phandles
A SerDes can host multiple PCS links: QSGMII binds four ports to one
SerDes, USXGMII variants up to eight. Today pcs-handle references the
SerDes as a whole, with no way to express which link inside the SerDes
a port wants. The driver gets away with this because it carries its own
port->link bookkeeping and the link slot is implicit in DSA's port
iteration order -- functional, but the wiring information lives nowhere
in DT.

The upcoming fwnode_pcs migration moves PCS lookup to the generic
fwnode provider API, which disambiguates multiple instances per fwnode
via phandle cells. To make that landable as small, code-only commits,
the DT needs to carry the link index ahead of time.

Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs
and append the link cell to every pcs-handle reference across boards
and the SWITCH_PORT_* macros. Cell values match the existing wiring:
0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link
USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the
RTL9311 octal USXGMII layout.

No code reads the new cell yet -- of_parse_phandle_with_args() in the
PCS driver already cooperates with cells = 0 or 1, and the DSA glue
uses of_parse_phandle() which ignores cells entirely. The change is
runtime-neutral on its own; it exists so the follow-up code patches
can be a few lines each instead of dragging a bridge counter into the
driver to invent slot numbers DT could have provided directly.

Link: https://github.com/openwrt/openwrt/pull/23539
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
2026-05-31 12:52:40 +02:00

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// SPDX-License-Identifier: GPL-2.0-or-later
/dts-v1/;
#include "rtl930x.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
compatible = "plasmacloud,mcx3", "realtek,rtl9302-soc";
model = "Plasma Cloud MCX3";
chosen {
/* get active mtdparts from u-boot */
/delete-property/ bootargs;
};
aliases {
led-boot = &led_power;
led-running = &led_power;
led-failsafe = &led_power;
led-upgrade = &led_power;
label-mac-device = &ethernet0;
};
memory@0 {
reg = <0x0 0x10000000>;
};
keys {
compatible = "gpio-keys";
mode {
label = "reset";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
i2c0: i2c-gpio0 {
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
sda-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <5>; /* ~100 kHz */
};
sfp0: sfp-lan3 {
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio0 22 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_disable_sys_led>;
led_power: led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_POWER;
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-1 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
led_set@0 {
compatible = "realtek,rtl9300-leds";
active-low;
led_set0 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_5G |
RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_1G |
RTL93XX_LED_SET_100M | RTL93XX_LED_SET_10M |
RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
};
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0xe0000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0xe0000 0x10000>;
nvmem-layout {
compatible = "u-boot,env";
macaddr_ubootenv_ethaddr: ethaddr {
#nvmem-cell-cells = <1>;
};
};
};
partition@f0000 {
label = "u-boot-env2";
reg = <0xf0000 0x10000>;
};
partition@100000 {
label = "firmware1";
reg = <0x100000 0xf80000>;
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <0x93000000>;
};
partition@1080000 {
label = "firmware2";
reg = <0x1080000 0xf80000>;
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <0x93000000>;
};
};
};
};
&ethernet0 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
};
&mdio_bus0 {
reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <100000>;
PHY_C45(0, 0)
PHY_C45(1, 1)
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT_SDS(0, 2, 2, 0, 10g-qxgmii)
SWITCH_PORT_SDS(1, 1, 2, 1, 10g-qxgmii)
SWITCH_PORT_SFP(26, 3, 8, 0, 0)
/* CPU-port */
port@28 {
ethernet = <&ethernet0>;
reg = <28>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&port0 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 2>;
nvmem-cell-names = "mac-address";
};
&port1 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 1>;
nvmem-cell-names = "mac-address";
};
&port26 {
nvmem-cells = <&macaddr_ubootenv_ethaddr 3>;
nvmem-cell-names = "mac-address";
};