43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
311 lines
6.5 KiB
Plaintext
311 lines
6.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "hasivo,s600wp-5gt-2sx-se";
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model = "Hasivo S600WP-5GT-2SX-SE";
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x08000000>; /* 128 MiB */
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};
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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label-mac-device = ðernet0;
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};
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chosen {
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stdout-path = "serial0:38400n8";
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};
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keys {
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compatible = "gpio-keys";
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button-reset {
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label = "reset";
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gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>, <&pinmux_enable_led_sync>;
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led_sys: led-0 {
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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linux,default-trigger = "heartbeat";
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};
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};
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led_set {
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compatible = "realtek,rtl9300-leds";
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/* Port 25 is unused but present in the HC595 shift
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* register chain. Force it into the serial LED stream
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* to align all LED positions correctly.
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*/
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realtek,led-set0-force-port-mask = <(1 << 25)>;
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/*
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* RJ45 LED0 (green): 1G/LINK/ACT
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* RJ45 LED1 (green): 10M/100M/LINK/ACT
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* RJ45 LED2 (orange): 2.5G/LINK/ACT
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*/
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led_set0 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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/*
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* SFP+ LED0: 10G/LINK/ACT
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* SFP+ LED1: 1G/LINK/ACT
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* SFP+ LED2: spacer to keep 3 slots per port
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*/
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led_set1 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_NONE)>;
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};
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/*
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* TODO: I2C bus to the on-board HS104 PSE controller (PoE).
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* Defined here for documentation/future use; currently unused
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* because PSE/PoE support for this board is not yet wired up.
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*/
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i2c_scl23_sda22: i2c-scl23-sda22 {
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compatible = "i2c-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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i2c_sfp0: i2c-sfp0 {
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compatible = "i2c-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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scl-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <50>;
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};
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i2c_sfp1: i2c-sfp1 {
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compatible = "i2c-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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scl-gpios = <&gpio0 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <50>;
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};
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sfp0: sfp-p26 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp0>;
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mod-def0-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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tx-disable-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
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maximum-power-milliwatt = <2500>;
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};
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sfp1: sfp-p27 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp1>;
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mod-def0-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <2500>;
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/*
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* Stock firmware wires tx-disable to GPIO 12 (FB_TXDIS_1).
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* The pin is not claimed by the hardware I2C controller
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* (SDA pinmux is in GPIO mode) but still cannot be driven
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* HIGH for unknown reasons. Omitted for now.
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*/
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "fudan,fm25q128", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* stock is LOADER */
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partition@0 {
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label = "u-boot";
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reg = <0x0000000 0x00e0000>;
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read-only;
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};
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/* stock is BDINFO */
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partition@e0000 {
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label = "u-boot-env";
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reg = <0x00e0000 0x0010000>;
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nvmem-layout {
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compatible = "u-boot,env";
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macaddr_ubootenv_ethaddr: ethaddr {
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#nvmem-cell-cells = <1>;
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};
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serialnumber_ubootenv: serialnumber {
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#nvmem-cell-cells = <1>;
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};
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pse_bt_port_no_ubootenv: pse_bt_port_no {
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#nvmem-cell-cells = <1>;
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};
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pse_existed_flag_ubootenv: pse_existed_flag {
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#nvmem-cell-cells = <1>;
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};
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pse_power_bank_ubootenv: pse_power_bank {
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#nvmem-cell-cells = <1>;
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};
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};
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};
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/* stock is SYSINFO */
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partition@f0000 {
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label = "u-boot-env2";
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reg = <0x00f0000 0x0010000>;
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read-only;
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};
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/* stock is JFFS2_CFG */
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partition@100000 {
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label = "jffs";
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reg = <0x0100000 0x0100000>;
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};
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/* stock is JFFS2_LOG */
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partition@200000 {
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label = "jffs2";
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reg = <0x0200000 0x0100000>;
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};
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/* stock is RUNTIME */
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partition@300000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x0300000 0x0c00000>;
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};
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/* stock is OEMINFO */
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partition@f00000 {
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label = "oeminfo";
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reg = <0x0f00000 0x0100000>;
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read-only;
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
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nvmem-cell-names = "mac-address";
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};
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&mdio_bus0 {
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/* External RTL8221B PHYs */
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PHY_C45(0, 1)
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PHY_C45(8, 2)
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PHY_C45(16, 3)
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PHY_C45(20, 4)
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};
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&mdio_bus1 {
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/* External RTL8221B PHY */
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PHY_C45(24, 1)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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pcs-handle = <&serdes2 0>;
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phy-handle = <&phy0>;
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phy-mode = "sgmii";
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managed = "in-band-status";
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led-set = <0>;
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};
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port@8 {
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reg = <8>;
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label = "lan2";
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pcs-handle = <&serdes3 0>;
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phy-handle = <&phy8>;
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phy-mode = "sgmii";
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managed = "in-band-status";
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led-set = <0>;
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};
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port@16 {
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reg = <16>;
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label = "lan3";
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pcs-handle = <&serdes4 0>;
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phy-handle = <&phy16>;
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phy-mode = "sgmii";
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managed = "in-band-status";
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led-set = <0>;
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};
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port@20 {
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reg = <20>;
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label = "lan4";
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pcs-handle = <&serdes5 0>;
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phy-handle = <&phy20>;
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phy-mode = "sgmii";
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managed = "in-band-status";
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led-set = <0>;
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};
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port@24 {
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reg = <24>;
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label = "lan5";
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pcs-handle = <&serdes6 0>;
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phy-handle = <&phy24>;
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phy-mode = "sgmii";
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managed = "in-band-status";
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led-set = <0>;
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};
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SWITCH_PORT_SFP(26, 6, 8, 1, 0)
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SWITCH_PORT_SFP(27, 7, 9, 1, 1)
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/* Internal SoC */
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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