43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
406 lines
7.5 KiB
Plaintext
406 lines
7.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "macros.dtsi"
|
|
#include <dt-bindings/clock/rtl83xx-clk.h>
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
compatible = "realtek,rtl839x-soc";
|
|
|
|
osc: oscillator {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <25000000>;
|
|
};
|
|
|
|
ccu: clock-controller {
|
|
compatible = "realtek,rtl8390-clock";
|
|
#clock-cells = <1>;
|
|
clocks = <&osc>;
|
|
clock-names = "ref_clk";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "mips,mips34Kc";
|
|
reg = <0>;
|
|
clocks = <&ccu CLK_CPU>;
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "mips,mips34Kc";
|
|
reg = <1>;
|
|
clocks = <&ccu CLK_CPU>;
|
|
operating-points-v2 = <&cpu_opp_table>;
|
|
};
|
|
};
|
|
|
|
cpu_opp_table: opp-table-0 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <425000000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <450000000>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <475000000>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <525000000>;
|
|
};
|
|
opp05 {
|
|
opp-hz = /bits/ 64 <550000000>;
|
|
};
|
|
opp06 {
|
|
opp-hz = /bits/ 64 <575000000>;
|
|
};
|
|
opp07 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
};
|
|
opp08 {
|
|
opp-hz = /bits/ 64 <625000000>;
|
|
};
|
|
opp09 {
|
|
opp-hz = /bits/ 64 <650000000>;
|
|
};
|
|
opp10 {
|
|
opp-hz = /bits/ 64 <675000000>;
|
|
};
|
|
opp11 {
|
|
opp-hz = /bits/ 64 <700000000>;
|
|
};
|
|
opp12 {
|
|
opp-hz = /bits/ 64 <725000000>;
|
|
};
|
|
opp13 {
|
|
opp-hz = /bits/ 64 <750000000>;
|
|
};
|
|
};
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "earlycon";
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
cpuintc: cpuintc {
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
soc: soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x18000000 0x10000>;
|
|
|
|
intc: interrupt-controller@3000 {
|
|
compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
|
|
reg = <0x3000 0x18>, <0x3018 0x18>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>, <3>, <4>, <5>, <6>;
|
|
};
|
|
|
|
spi0: spi@1200 {
|
|
compatible = "realtek,rtl8380-spi";
|
|
reg = <0x1200 0x100>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
timer0: timer@3100 {
|
|
compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
|
|
reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
|
|
<0x3130 0x10>, <0x3140 0x10>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
|
|
clocks = <&ccu CLK_LXB>;
|
|
};
|
|
|
|
uart0: uart@2000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x2000 0x100>;
|
|
|
|
clocks = <&ccu CLK_LXB>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <31 1>;
|
|
|
|
reg-io-width = <1>;
|
|
reg-shift = <2>;
|
|
fifo-size = <1>;
|
|
no-loopback-test;
|
|
};
|
|
|
|
uart1: uart@2100 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&enable_uart1>;
|
|
|
|
compatible = "ns16550a";
|
|
reg = <0x2100 0x100>;
|
|
|
|
clocks = <&ccu CLK_LXB>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <30 2>;
|
|
|
|
reg-io-width = <1>;
|
|
reg-shift = <2>;
|
|
fifo-size = <1>;
|
|
no-loopback-test;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio-controller@3500 {
|
|
compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
|
|
reg = <0x3500 0x20>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <24>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <23 2>;
|
|
};
|
|
|
|
watchdog0: watchdog@3150 {
|
|
compatible = "realtek,rtl8390-wdt";
|
|
reg = <0x3150 0xc>;
|
|
|
|
realtek,reset-mode = "soc";
|
|
|
|
clocks = <&ccu CLK_LXB>;
|
|
timeout-sec = <30>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupt-names = "phase1", "phase2";
|
|
interrupts = <19 4>, <18 4>;
|
|
};
|
|
|
|
};
|
|
|
|
switchcore@1b000000 {
|
|
compatible = "syscon", "simple-mfd";
|
|
reg = <0x1b000000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ethernet0: ethernet {
|
|
compatible = "realtek,rtl8392-eth";
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <24 3>;
|
|
#interrupt-cells = <1>;
|
|
phy-mode = "internal";
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
|
|
mdio_ctrl: mdio-controller {
|
|
compatible = "realtek,rtl8392-mdio", "realtek,otto-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
mdio_bus0: mdio-bus@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
mdio_bus1: mdio-bus@1 {
|
|
reg = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
mdio_aux: mdio-aux {
|
|
compatible = "realtek,rtl8390-aux-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mdio_aux_mdx>;
|
|
};
|
|
|
|
mdio_serdes: mdio-serdes {
|
|
compatible = "realtek,rtl8392-serdes-mdio", "realtek,otto-serdes-mdio";
|
|
};
|
|
|
|
pcs {
|
|
compatible = "realtek,rtl8392-pcs", "realtek,otto-pcs";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
serdes0: serdes@0 {
|
|
reg = <0>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes1: serdes@1 {
|
|
reg = <1>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes2: serdes@2 {
|
|
reg = <2>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes3: serdes@3 {
|
|
reg = <3>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes4: serdes@4 {
|
|
reg = <4>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes5: serdes@5 {
|
|
reg = <5>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes6: serdes@6 {
|
|
reg = <6>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes7: serdes@7 {
|
|
reg = <7>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes8: serdes@8 {
|
|
reg = <8>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes9: serdes@9 {
|
|
reg = <9>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes10: serdes@10 {
|
|
reg = <10>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes11: serdes@11 {
|
|
reg = <11>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes12: serdes@12 {
|
|
reg = <12>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
serdes13: serdes@13 {
|
|
reg = <13>;
|
|
#pcs-cells = <1>;
|
|
};
|
|
};
|
|
|
|
soc_thermal: thermal {
|
|
compatible = "realtek,rtl8390-thermal";
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
switch0: ethernet-switch {
|
|
compatible = "realtek,rtl8392-switch", "realtek,otto-switch";
|
|
status = "okay";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <20 2>;
|
|
};
|
|
};
|
|
|
|
pinmux@1b000004 {
|
|
compatible = "pinctrl-single";
|
|
reg = <0x1b000004 0x4>;
|
|
|
|
pinctrl-single,bit-per-mux;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x1>;
|
|
#pinctrl-cells = <2>;
|
|
|
|
enable_uart1: pinmux_enable_uart1 {
|
|
pinctrl-single,bits = <0x0 0x1 0x3>;
|
|
};
|
|
|
|
disable_jtag: pinmux_disable_jtag {
|
|
pinctrl-single,bits = <0x0 0x2 0x3>;
|
|
};
|
|
};
|
|
|
|
/* LED_GLB_CTRL */
|
|
pinmux@1b0000e4 {
|
|
compatible = "pinctrl-single";
|
|
reg = <0x1b0000e4 0x4>;
|
|
|
|
pinctrl-single,bit-per-mux;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x1>;
|
|
#pinctrl-cells = <2>;
|
|
|
|
/* enable GPIO 0 */
|
|
pinmux_disable_sys_led: disable_sys_led {
|
|
pinctrl-single,bits = <0x0 0x0 0x4000>;
|
|
};
|
|
|
|
/* enable AUX MDC/MDIO */
|
|
mdio_aux_mdx: aux-mdx-pins {
|
|
pinctrl-single,bits = <0x0 0x100000 0x1c0000>;
|
|
};
|
|
|
|
/* disable port LED offloading */
|
|
port_led_offload: port-led-offload {
|
|
pinctrl-single,bits = <0x0 0x0 0x20>;
|
|
};
|
|
};
|
|
|
|
sram0: sram@9f000000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x9f000000 0x18000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x9f000000 0x18000>;
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
cpu-thermal {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <1000>;
|
|
coefficients = <1000 0>;
|
|
thermal-sensors = <&soc_thermal>;
|
|
trips {
|
|
cpu-crit {
|
|
temperature = <105000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|