43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
91 lines
2.0 KiB
Plaintext
91 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl8380_zyxel_gs1900.dtsi"
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#include "rtl8380_zyxel_gs1900_gpio.dtsi"
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/ {
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compatible = "zyxel,gs1900-10hp-a1", "realtek,rtl838x-soc";
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model = "Zyxel GS1900-10HP A1 Switch";
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/* i2c of the left SFP cage: port 9 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
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#thermal-sensor-cells = <0>;
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};
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/* i2c of the right SFP cage: port 10 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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#thermal-sensor-cells = <0>;
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};
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};
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&uart1 {
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status = "okay";
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};
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&switch0 {
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ethernet-ports {
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port@24 {
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reg = <24>;
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label = "lan9";
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pcs-handle = <&serdes4 0>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan10";
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pcs-handle = <&serdes5 0>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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};
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};
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&thermal_zones {
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sfp-thermal {
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polling-delay-passive = <10000>;
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polling-delay = <10000>;
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thermal-sensors = <&sfp0>, <&sfp1>;
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trips {
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sfp-crit {
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temperature = <110000>;
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hysteresis = <1000>;
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type = "critical";
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};
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};
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};
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};
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