43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
312 lines
7.0 KiB
Plaintext
312 lines
7.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later or MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "rtl930x.dtsi"
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/ {
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compatible = "d-link,dgs-1250-28x", "realtek,rtl9301-soc";
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model = "D-Link DGS-1250-28X";
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aliases {
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label-mac-device = ðernet0;
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led-boot = &led_power;
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led-failsafe = &led_console;
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led-running = &led_power;
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led-upgrade = &led_console;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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fan: gpio-fan {
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compatible = "gpio-fan";
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gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
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alarm-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
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/* simple on/off values as LM75 alert pin steers fan high/low speed */
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gpio-fan,speed-map = <0 0>, <1 1>;
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#cooling-cells = <2>;
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};
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i2c-gpio-shared {
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compatible = "i2c-gpio-shared";
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scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c0: i2c@0 {
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sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <5>;
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};
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i2c1: i2c@1 {
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sda-gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <5>;
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};
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i2c2: i2c@2 {
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sda-gpios = <&gpio0 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <5>;
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};
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i2c3: i2c@3 {
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sda-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <5>;
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};
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};
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i2c4: i2c-gpio-4 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio1: gpio-expander@20 {
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compatible = "nxp,pca9555";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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temperature_sensor: temperature-sensor@48 {
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compatible = "microchip,tcn75";
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reg = <0x48>;
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#thermal-sensor-cells = <0>;
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ti,alert-polarity-active-high;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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mac_address: mac-address@10 {
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reg = <0x10 0x6>;
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};
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};
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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/*
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* 1G Ports LED0 (green): 1G/LINK/ACT
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* 1G Ports LED1 (orange): 10M/100M/LINK/ACT
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*/
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led_set0 = <(RTL93XX_LED_SET_1G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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/*
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* 10G Ports LED0 (green): 10G/LINK/ACT
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* 10G Ports LED1 (orange): 10M/100M/1G/2.5G/5G/LINK/ACT
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*/
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led_set1 = <(RTL93XX_LED_SET_10G | RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)
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(RTL93XX_LED_SET_10M | RTL93XX_LED_SET_100M | RTL93XX_LED_SET_1G |
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RTL93XX_LED_SET_2P5G | RTL93XX_LED_SET_5G |
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RTL93XX_LED_SET_LINK | RTL93XX_LED_SET_ACT)>;
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};
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leds: leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-leds";
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led_power: led-0 {
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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};
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led_console: led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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};
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led_fault: led-2 {
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function = LED_FUNCTION_FAULT;
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color = <LED_COLOR_ID_RED>;
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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};
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};
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sfp0: sfp-p24 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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mod-def0-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p25 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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mod-def0-gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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};
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sfp2: sfp-p26 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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sfp3: sfp-p27 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c3>;
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mod-def0-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x100000 0x80000>;
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};
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partition@180000 {
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label = "u-boot-env2";
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reg = <0x180000 0x80000>;
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};
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partition@200000 {
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label = "firmware";
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compatible = "openwrt,uimage";
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reg = <0x200000 0x3e00000>;
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};
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};
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};
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};
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&mdio_bus0 {
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PHY_C22(0, 0)
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PHY_C22(1, 1)
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PHY_C22(2, 2)
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PHY_C22(3, 3)
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PHY_C22(4, 4)
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PHY_C22(5, 5)
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PHY_C22(6, 6)
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PHY_C22(7, 7)
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};
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&mdio_bus1 {
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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};
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&mdio_bus2 {
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PHY_C22(16, 16)
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PHY_C22(17, 17)
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PHY_C22(18, 18)
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PHY_C22(19, 19)
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PHY_C22(20, 20)
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PHY_C22(21, 21)
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PHY_C22(22, 22)
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PHY_C22(23, 23)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT_LED(0, 1, 0, 0, 0, qsgmii)
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SWITCH_PORT_LED(1, 2, 0, 1, 0, qsgmii)
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SWITCH_PORT_LED(2, 3, 0, 2, 0, qsgmii)
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SWITCH_PORT_LED(3, 4, 0, 3, 0, qsgmii)
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SWITCH_PORT_LED(4, 5, 1, 0, 0, qsgmii)
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SWITCH_PORT_LED(5, 6, 1, 1, 0, qsgmii)
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SWITCH_PORT_LED(6, 7, 1, 2, 0, qsgmii)
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SWITCH_PORT_LED(7, 8, 1, 3, 0, qsgmii)
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SWITCH_PORT_LED(8, 9, 2, 0, 0, usxgmii)
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SWITCH_PORT_LED(9, 10, 2, 1, 0, usxgmii)
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SWITCH_PORT_LED(10, 11, 2, 2, 0, usxgmii)
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SWITCH_PORT_LED(11, 12, 2, 3, 0, usxgmii)
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SWITCH_PORT_LED(12, 13, 2, 4, 0, usxgmii)
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SWITCH_PORT_LED(13, 14, 2, 5, 0, usxgmii)
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SWITCH_PORT_LED(14, 15, 2, 6, 0, usxgmii)
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SWITCH_PORT_LED(15, 16, 2, 7, 0, usxgmii)
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SWITCH_PORT_LED(16, 17, 3, 0, 0, usxgmii)
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SWITCH_PORT_LED(17, 18, 3, 1, 0, usxgmii)
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SWITCH_PORT_LED(18, 19, 3, 2, 0, usxgmii)
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SWITCH_PORT_LED(19, 20, 3, 3, 0, usxgmii)
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SWITCH_PORT_LED(20, 21, 3, 4, 0, usxgmii)
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SWITCH_PORT_LED(21, 22, 3, 5, 0, usxgmii)
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SWITCH_PORT_LED(22, 23, 3, 6, 0, usxgmii)
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SWITCH_PORT_LED(23, 24, 3, 7, 0, usxgmii)
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SWITCH_PORT_SFP(24, 25, 4, 1, 0)
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SWITCH_PORT_SFP(25, 26, 6, 1, 1)
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SWITCH_PORT_SFP(26, 27, 8, 1, 2)
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SWITCH_PORT_SFP(27, 28, 9, 1, 3)
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port@28 {
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reg = <28>;
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ethernet = <ðernet0>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&mac_address>;
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nvmem-cell-names = "mac-address";
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};
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