A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
220 lines
4.0 KiB
Plaintext
220 lines
4.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "rtl838x.dtsi"
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/ {
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compatible = "linksys,lgs310c", "realtek,rtl838x-soc";
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model = "Linksys LGS310C";
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aliases {
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label-mac-device = ðernet0;
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led-boot = &led_power;
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led-failsafe = &led_fault;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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leds: leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-leds";
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led_power: led-0 {
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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};
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led_fault: led-1 {
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function = LED_FUNCTION_FAULT;
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color = <LED_COLOR_ID_AMBER>;
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
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};
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};
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i2c-gpio-shared {
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compatible = "i2c-gpio-shared";
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c0: i2c@0 {
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sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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i2c1: i2c@1 {
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sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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};
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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ðernet0 {
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nvmem-cells = <&macaddr_ubootenv_ethaddr 0>;
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nvmem-cell-names = "mac-address";
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};
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&mdio_aux {
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status = "okay";
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gpio1: expander@0 {
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compatible = "realtek,rtl8231";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio1 0 0 37>;
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led-controller {
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compatible = "realtek,rtl8231-leds";
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status = "disabled";
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x00000000 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x00080000 0x10000>;
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nvmem-layout {
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compatible = "u-boot,env";
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macaddr_ubootenv_ethaddr: ethaddr {
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@90000 {
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label = "u-boot-env2";
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reg = <0x00090000 0x10000>;
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};
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partition@a0000 {
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label = "jffs2";
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reg = <0x000a0000 0x500000>;
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};
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partition@5a0000 {
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label = "firmware";
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compatible = "openwrt,uimage";
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reg = <0x005a0000 0xd30000>;
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};
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partition@2d0000 {
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label = "kernel2";
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reg = <0x012d0000 0xd30000>;
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};
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};
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};
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};
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&uart1 {
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status = "okay";
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};
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&mdio_bus0 {
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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port@24 {
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reg = <24>;
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label = "lan9";
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pcs-handle = <&serdes4 0>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan10";
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pcs-handle = <&serdes5 0>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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