43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
91 lines
2.1 KiB
Plaintext
91 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl9313_zyxel_xs1930-aqr813.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/mux/mux.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "zyxel,xs1930-12hp", "realtek,rtl9313-soc";
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model = "Zyxel XS1930-12HP";
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leds {
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led_poe_max: led-7 {
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color = <LED_COLOR_ID_RED>;
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function = "poe-usage";
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gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&led_set {
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/* Phantom port chain padding (2 LEDs) */
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led_set1 = <RTL93XX_LED_SET_NONE
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RTL93XX_LED_SET_NONE>;
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/* The LED PCB has two daisy-chained RTL8231 in scan mode.
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* Net LEDs for P3-P12 are on the first RTL8231, P1/P2
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* net LEDs are on the second. The 12 real ports provide
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* 36 LED bits but the chain requires 65 bits to correctly
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* span both chips. Phantom ports 1-7, 9-10 (set0, 3 LEDs
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* each) and port 11 (set1, 2 LEDs) pad the chain with
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* the remaining 29 bits.
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*/
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realtek,led-set0-force-port-mask = <0x00000000 0x000006FE>;
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realtek,led-set1-force-port-mask = <0x00000000 0x00000800>;
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};
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&led_sys_green { gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; };
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&led_sys_red { gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; };
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&gpio0 {
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poe_enable_hog {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-enable";
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};
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};
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&i2c_mst1 {
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/* PoE management MCU sits here */
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i2c3: i2c@3 { reg = <3>; };
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};
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&mdio_ctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_enable_mdc_mdio_0>,
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<&pinmux_enable_mdc_mdio_1>,
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<&pinmux_enable_mdc_mdio_2>;
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};
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&mdio_bus1 {
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PHY_C45(52, 0) /* AQR113C */
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};
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&mdio_bus2 {
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PHY_C45(53, 8) /* AQR113C */
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};
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&switch0 {
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ethernet-ports {
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/* Copper ports behind AQR113C */
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SWITCH_PORT_LED(52, 9, 10, 0, 0, usxgmii)
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SWITCH_PORT_LED(53, 10, 11, 0, 0, usxgmii)
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SWITCH_PORT_SFP(54, 11, 12, 0, 1)
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SWITCH_PORT_SFP(55, 12, 13, 0, 2)
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};
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};
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&port52 { managed = "in-band-status"; };
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&port53 { managed = "in-band-status"; };
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&serdes10 { tx-polarity = <PHY_POL_INVERT>; };
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&serdes11 { tx-polarity = <PHY_POL_INVERT>; };
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