43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
78 lines
1.3 KiB
Plaintext
78 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "rtl8380_netgear_gigabit.dtsi"
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "netgear,gs310tp-v1", "realtek,rtl838x-soc";
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model = "Netgear GS310TP v1";
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aliases {
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led-boot = &led_power_green;
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led-failsafe = &led_power_amber;
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led-running = &led_power_green;
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led-upgrade = &led_power_amber;
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};
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leds {
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compatible = "gpio-leds";
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led_power_amber: led-0 {
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
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};
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led_power_green: led-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&gpio1 {
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poe-enable {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "poe-enable";
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};
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};
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&firmware {
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openwrt,ih-magic = <0x4e474335>;
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};
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&uart1 {
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status = "okay";
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};
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&switch0 {
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ethernet-ports {
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/* TODO: fixed link SFP is not right */
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port24: port@24 {
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reg = <24>;
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label = SWITCH_PORT_LABEL(9);
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pcs-handle = <&serdes4 0>;
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phy-mode = "1000base-x";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port26: port@26 {
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reg = <26>;
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label = SWITCH_PORT_LABEL(10);
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pcs-handle = <&serdes5 0>;
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phy-mode = "1000base-x";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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