43562f97e7
A SerDes can host multiple PCS links: QSGMII binds four ports to one SerDes, USXGMII variants up to eight. Today pcs-handle references the SerDes as a whole, with no way to express which link inside the SerDes a port wants. The driver gets away with this because it carries its own port->link bookkeeping and the link slot is implicit in DSA's port iteration order -- functional, but the wiring information lives nowhere in DT. The upcoming fwnode_pcs migration moves PCS lookup to the generic fwnode provider API, which disambiguates multiple instances per fwnode via phandle cells. To make that landable as small, code-only commits, the DT needs to carry the link index ahead of time. Bump #pcs-cells from 0 to 1 on every SerDes node in the four SoC DTSIs and append the link cell to every pcs-handle reference across boards and the SWITCH_PORT_* macros. Cell values match the existing wiring: 0 for single-link SerDes (10GBase-R, SGMII, fiber, single-link USXGMII), 0..3 per SerDes for QSGMII and USXGMII-QX, 0..7 for the RTL9311 octal USXGMII layout. No code reads the new cell yet -- of_parse_phandle_with_args() in the PCS driver already cooperates with cells = 0 or 1, and the DSA glue uses of_parse_phandle() which ignores cells entirely. The change is runtime-neutral on its own; it exists so the follow-up code patches can be a few lines each instead of dragging a bridge counter into the driver to invent slot numbers DT could have provided directly. Link: https://github.com/openwrt/openwrt/pull/23539 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
123 lines
2.4 KiB
Plaintext
123 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "panasonic,m8eg-pn28080k", "realtek,rtl8380-soc";
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model = "Panasonic Switch-M8eG PN28080K";
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aliases {
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led-boot = &led_status_eco_green;
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led-failsafe = &led_status_eco_amber;
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led-running = &led_status_eco_green;
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led-upgrade = &led_status_eco_green;
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
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los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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};
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&leds {
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led_status_eco_amber: led-5 {
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gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <1>;
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};
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led_status_eco_green: led-6 {
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gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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function-enumerator = <2>;
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};
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};
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&i2c_gpio_0 {
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scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&i2c_gpio_1 {
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scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&gpio1 {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gpio0>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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};
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&gpio2 {
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gpio0>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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};
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&i2c_switch {
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i2c0: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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};
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};
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&mdio_bus0 {
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PHY_C22(8, 8)
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PHY_C22(9, 9)
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PHY_C22(10, 10)
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PHY_C22(11, 11)
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PHY_C22(12, 12)
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PHY_C22(13, 13)
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PHY_C22(14, 14)
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PHY_C22(15, 15)
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};
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&switch0 {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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port@24 {
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reg = <24>;
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label = "lan9";
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pcs-handle = <&serdes4 0>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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