809ca978d1
Generate new patches for 6.18 from my ipq95xx development branch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21506 Signed-off-by: Robert Marko <robimarko@gmail.com>
537 lines
20 KiB
Diff
537 lines
20 KiB
Diff
From 9aa8c91d20f6cf1e97a3aa55788f4900970c3ad5 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Mon, 29 Jan 2024 17:57:20 +0800
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Subject: [PATCH] dt-bindings: net: Document Qualcomm QCA8084 PHY package
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QCA8084 is quad PHY chip, which integrates 4 PHYs, 2 PCS
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interfaces (PCS0 and PCS1) and clock controller, which can
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also be integrated to the switch chip named as QCA8386.
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1. MDIO address of 4 PHYs, 2 PCS and 1 XPCS (PCS1 includes
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PCS and XPCS, PCS0 includes PCS) can be configured.
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2. The package mode of PHY is optionally configured for the
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interface mode of two PCSes working correctly.
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3. The package level clock and reset need to be initialized.
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4. The clock and reset per PHY device need to be initialized
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so that the PHY register can be accessed.
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Change-Id: Idb2338d2673152cbd3c57e95968faa59e9d4a80f
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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Alex G: Update to match the patches that will be upstream.
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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.../devicetree/bindings/net/qcom,qca8084.yaml | 488 ++++++++++++++++++
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include/dt-bindings/net/qcom,qca808x.h | 14 +
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2 files changed, 502 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/qcom,qca8084.yaml
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create mode 100644 include/dt-bindings/net/qcom,qca808x.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/qcom,qca8084.yaml
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@@ -0,0 +1,488 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/net/qcom,qca8084.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm QCA8084 Ethernet Quad PHY
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+
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+maintainers:
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+ - Luo Jie <quic_luoj@quicinc.com>
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+
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+description:
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+ Qualcomm QCA8084 is PHY package of four-port Ethernet transceiver,
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+ the Ethernet port supports link speed 10/100/1000/2500 Mbps.
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+ There are two PCSes (PCS0 and PCS1) integrated in the PHY
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+ package, PCS1 includes XPCS and PCS to support the interface
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+ mode 10G-QXGMII and SGMII, PCS0 includes a PCS to support the
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+ interface mode SGMII only. There is also a clock controller
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+ integrated in the PHY package. This four-port Ethernet
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+ transceiver can also be integrated to the switch chip named
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+ as QCA8386. The PHY package mode needs to be configured as the
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+ correct value to apply the interface mode of two PCSes as
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+ mentioned below.
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+
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+ QCA8084 expects an input reference clock 50 MHZ as the clock
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+ source of the integrated clock controller, the integrated
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+ clock controller supplies the clocks and resets to the
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+ integrated PHY, PCS and PHY package.
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+
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+ - |
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+ +--| |--+-------------------+--| |--+
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+ | PCS1 |<------------+---->| PCS0 |
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+ +-------+ | +-------+
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+ | | |
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+ Ref 50M clk +--------+ | |
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+ ------------>| | clk & rst | |
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+ GPIO Reset |QCA8K-CC+------------+ |
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+ ------------>| | | |
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+ +--------+ | |
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+ | V |
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+ +--------+--------+--------+--------+
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+ | PHY0 | PHY1 | PHY2 | PHY3 |
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+ +--------+--------+--------+--------+
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+
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+properties:
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+ compatible:
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+ const: qcom,qca8084-package
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+
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+ clocks:
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+ description:
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+ PHY package level initial common clocks, which are needed to
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+ be enabled after GPIO reset on the PHY package, these clocks
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+ are supplied from the PHY integrated clock controller (QCA8K-CC).
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+ items:
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+ - description: APB bridge clock
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+ - description: AHB clock
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+ - description: Security control clock
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+ - description: TLMM clock
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+ - description: TLMM AHB clock
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+ - description: CNOC AHB clock
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+ - description: MDIO AHB clock
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+
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+ clock-names:
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+ items:
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+ - const: apb_bridge
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+ - const: ahb
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+ - const: sec_ctrl_ahb
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+ - const: tlmm
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+ - const: tlmm_ahb
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+ - const: cnoc_ahb
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+ - const: mdio_ahb
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+
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+ resets:
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+ description:
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+ PHY package level initial common reset, which are needed to
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+ be deasserted after GPIO reset on the PHY package, this reset
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+ is provided by the PHY integrated clock controller to do PHY
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+ DSP reset.
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+ maxItems: 1
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+
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+ qcom,package-mode:
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+ description: |
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+ The package mode of PHY supports to be configured as 3 modes
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+ to apply the combinations of interface mode of two PCSes
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+ correctly. This value should use one of the values defined in
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+ dt-bindings/net/qcom,qca808x.h. The package mode 10G-QXGMII of
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+ Quad PHY is used by default.
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+
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+ package mode PCS1 PCS0
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+ phy mode (0) 10G-QXGMII for not used
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+ PHY0-PHY3
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+
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+ switch mode (1) SGMII for SGMII for
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+ switch MAC0 switch MAC5 (optional)
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+
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+ switch bypass MAC5 (2) SGMII for SGMII for
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+ switch MAC0 PHY3
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+ $ref: /schemas/types.yaml#/definitions/uint32
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+ enum: [0, 1, 2]
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+ default: 0
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+
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+ qcom,phy-addr-fixup:
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+ description:
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+ MDIO address for PHY0-PHY3, PCS0 and PCS1 including PCS and XPCS,
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+ which can be optionally customized by programming the security
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+ control register of PHY package. The hardware default MDIO address
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+ of PHY0-PHY3, PCS0 and PCS1 including PCS and XPCS is 0-6.
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+ $ref: /schemas/types.yaml#/definitions/uint32-array
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+ minItems: 7
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+ maxItems: 7
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+
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+patternProperties:
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+ ^ethernet-phy@[a-f0-9]+$:
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+ unevaluatedProperties: false
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+ $ref: ethernet-phy.yaml#
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+
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+ properties:
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+ compatible:
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+ const: ethernet-phy-id004d.d180
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+
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+ qcom,xpcs-channel:
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+ description:
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+ When PCS1 works on the interface mode 10G-QXGMII, the integrated
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+ XPCS including 4 channels is used to connected with the Quad PHYs,
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+ each PHY needs to be specified the XPCS channel ID to deliver the
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+ PHY link status to the XPCS.
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+ $ref: /schemas/types.yaml#/definitions/uint32
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+ enum: [0, 1, 2, 3]
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+
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+ required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - resets
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+
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+ ^pcs-phy@[a-f0-9]+$:
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+ type: object
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+ additionalProperties: false
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+ description:
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+ PCS device has the independent MDIO address, which controls
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+ the interface mode used and provides the clocks such as
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+ 312.5 MHZ as RX and TX root clocks to the integrated clock
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+ controller.
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+ properties:
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+ compatible:
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+ const: qcom,qca8k-pcs-phy
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+
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+ reg:
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+ items:
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+ - description: PCS MDIO address.
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+
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+ clocks:
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+ items:
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+ - description: PCS clock.
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+ - description: PCS RX root clock.
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+ - description: PCS TX root clock.
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+
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+ clock-names:
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+ items:
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+ - const: pcs
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+ - const: pcs_rx_root
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+ - const: pcs_tx_root
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+
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+ resets:
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+ items:
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+ - description: PCS reset.
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+
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+ required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - resets
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+
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+ ^xpcs-phy@[a-f0-9]+$:
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+ type: object
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+ additionalProperties: false
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+ description:
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+ XPCS device has the independent MDIO address, which includes 4
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+ channels to connect with Quad PHYs.
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+ properties:
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+ compatible:
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+ const: qcom,qca8k-xpcs-phy
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+
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+ reg:
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+ items:
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+ - description: XPCS MDIO address.
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+
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+ resets:
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+ items:
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+ - description: XPCS reset.
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+
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+ '#address-cells':
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+ const: 1
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+
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+ '#size-cells':
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+ const: 0
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+
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+ required:
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+ - compatible
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+ - reg
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+ - resets
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+ - '#address-cells'
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+ - '#size-cells'
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+
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+ patternProperties:
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+ "^channel@[0-3]+$":
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+ type: object
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+ additionalProperties: false
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+ description:
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+ XPCS is used to support 10G-QXGMII mode, which inlcudes 4 channels
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+ to be connected with Quad PHYs, each channels has the dedicated
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+ clocks and resets from the integrated clock controller of QCA8084.
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+
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+ properties:
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+ reg:
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+ items:
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+ - description: XPCS channel ID
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+
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+ clocks:
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+ items:
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+ - description: XPCS XGMII RX clock
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+ - description: XPCS XGMII TX clock
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+ - description: XPCS RX clock
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+ - description: XPCS TX clock
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+ - description: Port RX clock
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+ - description: Port TX clock
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+ - description: RX source clock
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+ - description: TX source clock
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+
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+ clock-names:
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+ items:
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+ - const: xgmii_rx
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+ - const: xgmii_tx
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+ - const: xpcs_rx
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+ - const: xpcs_tx
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+ - const: port_rx
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+ - const: port_tx
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+ - const: rx_src
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+ - const: tx_src
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+
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+ resets:
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+ items:
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+ - description: XPCS XGMII RX reset
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+ - description: XPCS XGMII TX reset
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+ - description: XPCS RX reset
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+ - description: XPCS TX reset
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+ - description: Port RX reset
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+ - description: Port TX reset
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+
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+ reset-names:
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+ items:
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+ - const: xgmii_rx
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+ - const: xgmii_tx
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+ - const: xpcs_rx
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+ - const: xpcs_tx
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+ - const: port_rx
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+ - const: port_tx
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+
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+ required:
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+ - reset-names
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+
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+required:
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+ - compatible
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+ - clocks
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+ - clock-names
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+ - resets
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+
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+allOf:
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+ - $ref: ethernet-phy-package.yaml#
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,qca8k-nsscc.h>
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+ #include <dt-bindings/net/qcom,qca808x.h>
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+ #include <dt-bindings/reset/qcom,qca8k-nsscc.h>
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethernet-phy-package@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "qcom,qca8084-package";
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+ reg = <1>;
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+ clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
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+ <&qca8k_nsscc NSS_CC_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_TLMM_CLK>,
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+ <&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
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+ <&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>;
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+ clock-names = "apb_bridge",
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+ "ahb",
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+ "sec_ctrl_ahb",
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+ "tlmm",
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+ "tlmm_ahb",
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+ "cnoc_ahb",
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+ "mdio_ahb";
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY_FULL_ARES>;
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+ qcom,package-mode = <QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED>;
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+ qcom,phy-addr-fixup = <1 2 3 4 5 6 7>;
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+
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+ ethernet-phy@1 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <1>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>;
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+ qcom,xpcs-channel = <0>;
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+ };
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+
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+ ethernet-phy@2 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <2>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>;
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+ qcom,xpcs-channel = <1>;
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+ };
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+
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+ ethernet-phy@3 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <3>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>;
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+ qcom,xpcs-channel = <2>;
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+ };
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+
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+ ethernet-phy@4 {
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+ compatible = "ethernet-phy-id004d.d180";
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+ reg = <4>;
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+ clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>;
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+ resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>;
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+ qcom,xpcs-channel = <3>;
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+ };
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+
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+ pcs-phy@6 {
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+ compatible = "qcom,qca8k-pcs-phy";
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+ reg = <6>;
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+ clocks = <&qca8k_nsscc NSS_CC_SRDS1_SYS_CLK>,
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+ <&qca8k_uniphy1_tx312p5m>,
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+ <&qca8k_uniphy1_rx312p5m>;
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+ clock-names = "pcs", "pcs_rx_root", "pcs_tx_root";
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+ resets = <&qca8k_nsscc NSS_CC_SRDS1_SYS_ARES>;
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+ };
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+
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+ xpcs-phy@7 {
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+ compatible = "qcom,qca8k-xpcs-phy";
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+ reg = <7>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ resets = <&qca8k_nsscc NSS_CC_XPCS_ARES>;
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+
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+ channel@0 {
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+ reg = <0>;
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+ clocks = <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC1_RX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC1_TX_CLK_SRC>;
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+ clock-names = "xgmii_rx",
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+ "xgmii_tx",
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+ "xpcs_rx",
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+ "xpcs_tx",
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+ "port_rx",
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+ "port_tx",
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+ "rx_src",
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+ "tx_src";
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+ resets = <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_TX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC1_SRDS1_CH0_RX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_RX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC1_GEPHY0_TX_ARES>;
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+ reset-names = "xgmii_rx",
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+ "xgmii_tx",
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+ "xpcs_rx",
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+ "xpcs_tx",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ channel@1 {
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+ reg = <1>;
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+ clocks = <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_RX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_TX_CLK>,
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+ <&qca8k_nsscc NSS_CC_MAC2_RX_CLK_SRC>,
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+ <&qca8k_nsscc NSS_CC_MAC2_TX_CLK_SRC>;
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+ clock-names = "xgmii_rx",
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+ "xgmii_tx",
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+ "xpcs_rx",
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+ "xpcs_tx",
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+ "port_rx",
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+ "port_tx",
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+ "rx_src",
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+ "tx_src";
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+ resets = <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES>,
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+ <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_TX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC2_SRDS1_CH1_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC2_GEPHY1_TX_ARES>;
|
|
+ reset-names = "xgmii_rx",
|
|
+ "xgmii_tx",
|
|
+ "xpcs_rx",
|
|
+ "xpcs_tx",
|
|
+ "port_rx",
|
|
+ "port_tx";
|
|
+ };
|
|
+
|
|
+ channel@2 {
|
|
+ reg = <2>;
|
|
+ clocks = <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_TX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_RX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_RX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_TX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_RX_CLK_SRC>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_TX_CLK_SRC>;
|
|
+ clock-names = "xgmii_rx",
|
|
+ "xgmii_tx",
|
|
+ "xpcs_rx",
|
|
+ "xpcs_tx",
|
|
+ "port_rx",
|
|
+ "port_tx",
|
|
+ "rx_src",
|
|
+ "tx_src";
|
|
+ resets = <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_TX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_SRDS1_CH2_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC3_GEPHY2_TX_ARES>;
|
|
+ reset-names = "xgmii_rx",
|
|
+ "xgmii_tx",
|
|
+ "xpcs_rx",
|
|
+ "xpcs_tx",
|
|
+ "port_rx",
|
|
+ "port_tx";
|
|
+ };
|
|
+
|
|
+ channel@3 {
|
|
+ reg = <3>;
|
|
+ clocks = <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_TX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_RX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_RX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_TX_CLK>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_RX_CLK_SRC>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_TX_CLK_SRC>;
|
|
+ clock-names = "xgmii_rx",
|
|
+ "xgmii_tx",
|
|
+ "xpcs_rx",
|
|
+ "xpcs_tx",
|
|
+ "port_rx",
|
|
+ "port_tx",
|
|
+ "rx_src",
|
|
+ "tx_src";
|
|
+ resets = <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_TX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_SRDS1_CH3_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_RX_ARES>,
|
|
+ <&qca8k_nsscc NSS_CC_MAC4_GEPHY3_TX_ARES>;
|
|
+ reset-names = "xgmii_rx",
|
|
+ "xgmii_tx",
|
|
+ "xpcs_rx",
|
|
+ "xpcs_tx",
|
|
+ "port_rx",
|
|
+ "port_tx";
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/net/qcom,qca808x.h
|
|
@@ -0,0 +1,14 @@
|
|
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
|
+/*
|
|
+ * Device Tree constants for the Qualcomm QCA808X PHYs
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_QCOM_QCA808X_H
|
|
+#define _DT_BINDINGS_QCOM_QCA808X_H
|
|
+
|
|
+/* PHY package modes of QCA8084 to apply the interface modes of two PCSes. */
|
|
+#define QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED 0
|
|
+#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC 1
|
|
+#define QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_PHY 2
|
|
+
|
|
+#endif
|