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qualcommbe: kernel-6.18: update patches

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Generate new patches for 6.18 from my ipq95xx development branch.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21506
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2026-01-10 16:31:28 -06:00 committed by Robert Marko
parent 7ea10c7015
commit 809ca978d1
56 changed files with 3655 additions and 352 deletions
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2
target/linux/qualcommbe/patches-6.18/0301-dt-bindings-net-Document-Qualcomm-QCA8084-PHY-packag.patch
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@ -1,4 +1,4 @@
From 7b1c4e22532ded6b20ee41936fa38b5ca1e61ff9 Mon Sep 17 00:00:00 2001
From 9aa8c91d20f6cf1e97a3aa55788f4900970c3ad5 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Mon, 29 Jan 2024 17:57:20 +0800
Subject: [PATCH] dt-bindings: net: Document Qualcomm QCA8084 PHY package

14
target/linux/qualcommbe/patches-6.18/0302-net-phy-qca808x-Add-QCA8084-ethernet-phy-support.patch
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@ -1,4 +1,4 @@
From 60c44842f9611be237ab3f68afe8ebf2d9595fb2 Mon Sep 17 00:00:00 2001
From a4466aa8e02626f95910e0ef1484e62e57317e4e Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Thu, 6 Apr 2023 18:09:07 +0800
Subject: [PATCH] net: phy: qca808x: Add QCA8084 ethernet phy support
@ -46,7 +46,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
MODULE_LICENSE("GPL");
struct qca808x_priv {
@@ -153,13 +160,18 @@ static bool qca808x_is_prefer_master(str
@@ -154,13 +161,18 @@ static bool qca808x_is_prefer_master(str
static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
{
@ -66,7 +66,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
if (ret < 0)
return true;
@@ -273,6 +285,23 @@ static int qca808x_read_status(struct ph
@@ -278,6 +290,23 @@ static int qca808x_read_status(struct ph
return ret;
if (phydev->link) {
@ -90,7 +90,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
if (phydev->speed == SPEED_2500)
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
else
@@ -352,6 +381,18 @@ static int qca808x_cable_test_start(stru
@@ -357,6 +386,18 @@ static int qca808x_cable_test_start(stru
phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
@ -109,10 +109,10 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
return 0;
}
@@ -651,12 +692,32 @@ static struct phy_driver qca808x_driver[
.led_hw_control_set = qca808x_led_hw_control_set,
.led_hw_control_get = qca808x_led_hw_control_get,
@@ -674,12 +715,32 @@ static struct phy_driver qca808x_driver[
.led_polarity_set = qca808x_led_polarity_set,
.update_stats = qca808x_update_stats,
.get_phy_stats = qca808x_get_phy_stats,
+}, {
+ /* Qualcomm QCA8084 */
+ PHY_ID_MATCH_MODEL(QCA8084_PHY_ID),

8
target/linux/qualcommbe/patches-6.18/0303-net-phy-qca808x-Add-config_init-function-for-QCA8084.patch
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@ -1,4 +1,4 @@
From c052b9a4ab869cc54976402b3f9dbdef5bdb9f27 Mon Sep 17 00:00:00 2001
From eb7fa4e4886d8b5e3e832b63a6ca0c163961ffdf Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Wed, 8 Nov 2023 16:18:02 +0800
Subject: [PATCH] net: phy: qca808x: Add config_init function for QCA8084
@ -40,8 +40,8 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
MODULE_LICENSE("GPL");
@@ -663,6 +672,34 @@ static int qca808x_led_polarity_set(stru
active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
@@ -684,6 +693,34 @@ static void qca808x_get_phy_stats(struct
qcom_phy_get_stats(stats, priv->hw_stats);
}
+static int qca8084_config_init(struct phy_device *phydev)
@ -75,7 +75,7 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
static struct phy_driver qca808x_driver[] = {
{
/* Qualcomm QCA8081 */
@@ -711,6 +748,7 @@ static struct phy_driver qca808x_driver[
@@ -734,6 +771,7 @@ static struct phy_driver qca808x_driver[
.soft_reset = qca808x_soft_reset,
.cable_test_start = qca808x_cable_test_start,
.cable_test_get_status = qca808x_cable_test_get_status,

6
target/linux/qualcommbe/patches-6.18/0304-net-phy-qca808x-Add-link_change_notify-function-for-.patch
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@ -1,4 +1,4 @@
From aec49c172cd9c739c1d97ff2d42b9718bb20b609 Mon Sep 17 00:00:00 2001
From 1cc9a784c68b03bf1845214685f88ef519d917a2 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Wed, 8 Nov 2023 18:01:14 +0800
Subject: [PATCH] net: phy: qca808x: Add link_change_notify function for
@ -30,7 +30,7 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
MODULE_LICENSE("GPL");
@@ -700,6 +708,49 @@ static int qca8084_config_init(struct ph
@@ -721,6 +729,49 @@ static int qca8084_config_init(struct ph
QCA8084_MSE_THRESHOLD_2P5G_VAL);
}
@ -80,7 +80,7 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
static struct phy_driver qca808x_driver[] = {
{
/* Qualcomm QCA8081 */
@@ -749,6 +800,7 @@ static struct phy_driver qca808x_driver[
@@ -772,6 +823,7 @@ static struct phy_driver qca808x_driver[
.cable_test_start = qca808x_cable_test_start,
.cable_test_get_status = qca808x_cable_test_get_status,
.config_init = qca8084_config_init,

6
target/linux/qualcommbe/patches-6.18/0305-net-phy-qca808x-Add-register-access-support-routines.patch
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@ -1,4 +1,4 @@
From cea8043def0c0867370c2efd5a1cd73bf4d3e5ba Mon Sep 17 00:00:00 2001
From d6f61665d97cf1077ccbfff19c0df509b7c26aae Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Wed, 29 Nov 2023 15:21:22 +0800
Subject: [PATCH] net: phy: qca808x: Add register access support routines for
@ -44,8 +44,8 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
MODULE_LICENSE("GPL");
@@ -119,6 +135,78 @@ struct qca808x_priv {
int led_polarity_mode;
@@ -120,6 +136,78 @@ struct qca808x_priv {
struct qcom_phy_hw_stats hw_stats;
};
+static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page)

6
target/linux/qualcommbe/patches-6.18/0306-net-phy-qca808x-Add-QCA8084-probe-function.patch
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@ -1,4 +1,4 @@
From a7fe2c13f3188bf01b60fb15063d028c76dd2f1a Mon Sep 17 00:00:00 2001
From 5f58d9c84d96c6427e31373fe2b13eb8f6975769 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Mon, 29 Jan 2024 10:51:38 +0800
Subject: [PATCH] net: phy: qca808x: Add QCA8084 probe function
@ -73,7 +73,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
MODULE_LICENSE("GPL");
@@ -839,6 +858,78 @@ static void qca8084_link_change_notify(s
@@ -860,6 +879,78 @@ static void qca8084_link_change_notify(s
QCA8084_IPG_10_TO_11_EN : 0);
}
@ -152,7 +152,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
static struct phy_driver qca808x_driver[] = {
{
/* Qualcomm QCA8081 */
@@ -889,6 +980,7 @@ static struct phy_driver qca808x_driver[
@@ -912,6 +1003,7 @@ static struct phy_driver qca808x_driver[
.cable_test_get_status = qca808x_cable_test_get_status,
.config_init = qca8084_config_init,
.link_change_notify = qca8084_link_change_notify,

9
target/linux/qualcommbe/patches-6.18/0307-net-phy-qca808x-Add-package-clocks-and-resets-for-QC.patch
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@ -1,4 +1,4 @@
From 57379fe257895b374d35ce6578ecd62ce1cc1a4d Mon Sep 17 00:00:00 2001
From 3d5e5c940f98e6c627afe57123c4765c9306ca50 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Tue, 9 Apr 2024 16:30:55 +0800
Subject: [PATCH] net: phy: qca808x: Add package clocks and resets for QCA8084
@ -21,7 +21,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -150,10 +150,39 @@ MODULE_DESCRIPTION("Qualcomm Atheros QCA
@@ -150,11 +150,40 @@ MODULE_DESCRIPTION("Qualcomm Atheros QCA
MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
MODULE_LICENSE("GPL");
@ -40,6 +40,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+
struct qca808x_priv {
int led_polarity_mode;
struct qcom_phy_hw_stats hw_stats;
};
+struct qca808x_shared_priv {
@ -61,7 +62,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
static int __qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page)
{
return __mdiobus_write(bus, QCA8084_HIGH_ADDR_PREFIX | (sw_addr >> 5),
@@ -858,11 +887,24 @@ static void qca8084_link_change_notify(s
@@ -879,11 +908,24 @@ static void qca8084_link_change_notify(s
QCA8084_IPG_10_TO_11_EN : 0);
}
@ -87,7 +88,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Program the MDIO address of PHY and PCS optionally, the MDIO
* address 0-6 is used for PHY and PCS MDIO devices by default.
@@ -893,17 +935,43 @@ static int qca8084_phy_package_probe_onc
@@ -914,17 +956,43 @@ static int qca8084_phy_package_probe_onc
set |= FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]);
set |= FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6]);

10
target/linux/qualcommbe/patches-6.18/0308-net-phy-qca808x-Add-QCA8084-package-init-function.patch
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@ -1,4 +1,4 @@
From d39dc53424bcc778f1e468015490577e7bf0c7b6 Mon Sep 17 00:00:00 2001
From 7da15e71be92f1db476f631642cd1eb590102a43 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Thu, 25 Jan 2024 17:13:24 +0800
Subject: [PATCH] net: phy: qca808x: Add QCA8084 package init function
@ -39,7 +39,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
MODULE_LICENSE("GPL");
@@ -168,6 +175,7 @@ struct qca808x_priv {
@@ -169,6 +176,7 @@ struct qca808x_priv {
};
struct qca808x_shared_priv {
@ -47,8 +47,8 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
struct clk *clk[PACKAGE_CLK_MAX];
};
@@ -816,10 +824,111 @@ static int qca808x_led_polarity_set(stru
active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
@@ -837,10 +845,111 @@ static void qca808x_get_phy_stats(struct
qcom_phy_get_stats(stats, priv->hw_stats);
}
+static int qca8084_package_clock_init(struct qca808x_shared_priv *shared_priv)
@ -159,7 +159,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
__set_bit(PHY_INTERFACE_MODE_10G_QXGMII,
phydev->possible_interfaces);
@@ -954,6 +1063,15 @@ static int qca8084_phy_package_probe_onc
@@ -975,6 +1084,15 @@ static int qca8084_phy_package_probe_onc
shared_priv->clk[i] = clk;
}

61
target/linux/qualcommbe/patches-6.18/0309-net-phy-Add-phy_package_remove_once-helper.patch
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@ -1,4 +1,4 @@
From d11eba3e178a9d42a579c656b2c9b643f4ce3e1e Mon Sep 17 00:00:00 2001
From f3b0ae884a0b7e0a1e15fe188da278ed69a87b7c Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Mon, 23 Sep 2024 18:46:34 +0800
Subject: [PATCH] net: phy: Add phy_package_remove_once helper
@ -8,29 +8,52 @@ add phy_package_remove_once helper to support.
Change-Id: I3cd73bc7be1b1d531435ef72f48db0682548decf
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Alex G: Move phy_package_remove_once() to phy_package,c
Update to match the patches that will be upstream.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
include/linux/phy.h | 6 ++++++
1 file changed, 6 insertions(+)
drivers/net/phy/phy_package.c | 6 ++++++
drivers/net/phy/phylib.h | 1 +
drivers/net/phy/qcom/qca808x.c | 2 +-
3 files changed, 8 insertions(+), 1 deletion(-)
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -366,6 +366,7 @@ struct phy_package_shared {
/* used as bit number in atomic bitops */
#define PHY_SHARED_F_INIT_DONE 0
#define PHY_SHARED_F_PROBE_DONE 1
+#define PHY_SHARED_F_REMOVE_DONE 2
/**
* struct mii_bus - Represents an MDIO bus
@@ -2245,6 +2246,11 @@ static inline bool phy_package_probe_onc
return __phy_package_set_once(phydev, PHY_SHARED_F_PROBE_DONE);
--- a/drivers/net/phy/phy_package.c
+++ b/drivers/net/phy/phy_package.c
@@ -178,6 +178,12 @@ bool phy_package_probe_once(struct phy_d
}
EXPORT_SYMBOL_GPL(phy_package_probe_once);
+static inline bool phy_package_remove_once(struct phy_device *phydev)
+bool phy_package_remove_once(struct phy_device *phydev)
+{
+ return __phy_package_set_once(phydev, PHY_SHARED_F_REMOVE_DONE);
+ return __phy_package_set_once(phydev, 2);
+}
+EXPORT_SYMBOL_GPL(phy_package_remove_once);
+
extern const struct bus_type mdio_bus_type;
/**
* phy_package_join - join a common PHY group
* @phydev: target phy_device struct
--- a/drivers/net/phy/phylib.h
+++ b/drivers/net/phy/phylib.h
@@ -23,6 +23,7 @@ int __phy_package_write_mmd(struct phy_d
u32 regnum, u16 val);
bool phy_package_init_once(struct phy_device *phydev);
bool phy_package_probe_once(struct phy_device *phydev);
+bool phy_package_remove_once(struct phy_device *phydev);
int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size);
int of_phy_package_join(struct phy_device *phydev, size_t priv_size);
void phy_package_leave(struct phy_device *phydev);
--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
struct mdio_board_info {
-#include <dt-bindings/net/qcom,qca808x.h>
#include <linux/phy.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/reset.h>
#include <linux/clk.h>
+#include <dt-bindings/net/qcom,qca808x.h>
#include "../phylib.h"
#include "qcom.h"

23
target/linux/qualcommbe/patches-6.18/0310-net-phy-qca808x-Add-QCA8084-SerDes-probe-and-remove-.patch
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@ -1,4 +1,4 @@
From c12b79af730116936504afe97234f9afb6ac8fc0 Mon Sep 17 00:00:00 2001
From bc9732a26a25719475f2c6babb6968842cf97108 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Mon, 23 Sep 2024 20:28:24 +0800
Subject: [PATCH] net: phy: qca808x: Add QCA8084 SerDes probe and remove
@ -308,18 +308,19 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -8,6 +8,7 @@
#include <linux/clk.h>
#include <dt-bindings/net/qcom,qca808x.h>
#include "../phylib.h"
+#include "qca8084_serdes.h"
#include "qcom.h"
/* ADC threshold */
@@ -172,11 +173,13 @@ enum {
@@ -172,12 +173,14 @@ enum {
struct qca808x_priv {
int led_polarity_mode;
+ int channel_id;
struct qcom_phy_hw_stats hw_stats;
};
struct qca808x_shared_priv {
@ -329,7 +330,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
};
static const char *const qca8084_package_clk_name[PACKAGE_CLK_MAX] = {
@@ -354,6 +357,8 @@ static int qca808x_probe(struct phy_devi
@@ -355,6 +358,8 @@ static int qca808x_probe(struct phy_devi
{
struct device *dev = &phydev->mdio.dev;
struct qca808x_priv *priv;
@ -338,7 +339,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -362,6 +367,14 @@ static int qca808x_probe(struct phy_devi
@@ -363,6 +368,14 @@ static int qca808x_probe(struct phy_devi
/* Init LED polarity mode to -1 */
priv->led_polarity_mode = -1;
@ -353,7 +354,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
phydev->priv = priv;
return 0;
@@ -1012,6 +1025,7 @@ static int qca8084_phy_package_probe_onc
@@ -1033,6 +1046,7 @@ static int qca8084_phy_package_probe_onc
struct device_node *np = phy_package_get_node(phydev);
struct qca808x_shared_priv *shared_priv;
struct reset_control *rstc;
@ -361,7 +362,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
int i, ret, clear, set;
struct clk *clk;
@@ -1072,6 +1086,26 @@ static int qca8084_phy_package_probe_onc
@@ -1093,6 +1107,26 @@ static int qca8084_phy_package_probe_onc
if (ret && ret != -EINVAL)
return ret;
@ -388,7 +389,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
rstc = of_reset_control_get_exclusive(np, NULL);
if (IS_ERR(rstc))
return dev_err_probe(&phydev->mdio.dev, PTR_ERR(rstc),
@@ -1081,6 +1115,14 @@ static int qca8084_phy_package_probe_onc
@@ -1102,6 +1136,14 @@ static int qca8084_phy_package_probe_onc
return reset_control_deassert(rstc);
}
@ -403,7 +404,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
static int qca8084_probe(struct phy_device *phydev)
{
struct qca808x_shared_priv *shared_priv;
@@ -1099,6 +1141,10 @@ static int qca8084_probe(struct phy_devi
@@ -1120,6 +1162,10 @@ static int qca8084_probe(struct phy_devi
return ret;
}
@ -414,7 +415,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Enable clock of PHY device, so that the PHY register
* can be accessed to get PHY features.
*/
@@ -1116,6 +1162,12 @@ static int qca8084_probe(struct phy_devi
@@ -1137,6 +1183,12 @@ static int qca8084_probe(struct phy_devi
return reset_control_deassert(rstc);
}
@ -427,7 +428,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
static struct phy_driver qca808x_driver[] = {
{
/* Qualcomm QCA8081 */
@@ -1167,6 +1219,7 @@ static struct phy_driver qca808x_driver[
@@ -1190,6 +1242,7 @@ static struct phy_driver qca808x_driver[
.config_init = qca8084_config_init,
.link_change_notify = qca8084_link_change_notify,
.probe = qca8084_probe,

6
target/linux/qualcommbe/patches-6.18/0311-net-phy-qca808x-Add-QCA8084-SerDes-init-function.patch
View File

@ -1,4 +1,4 @@
From d137b725f8f4a7d49a809dcd73c5b836495ec44d Mon Sep 17 00:00:00 2001
From 94540ce4131c873e9294088f29230fdac8e97081 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Mon, 23 Sep 2024 20:59:40 +0800
Subject: [PATCH] net: phy: qca808x: Add QCA8084 SerDes init function
@ -419,7 +419,7 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
#endif /* _QCA8084_SERDES_H_ */
--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -926,6 +926,14 @@ static int qca8084_phy_package_config_in
@@ -947,6 +947,14 @@ static int qca8084_phy_package_config_in
usleep_range(10000, 11000);
@ -434,7 +434,7 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
/* Initialize the PHY package clock and reset, which is the
* necessary config sequence after GPIO reset on the PHY package.
*/
@@ -1164,6 +1172,9 @@ static int qca8084_probe(struct phy_devi
@@ -1185,6 +1193,9 @@ static int qca8084_probe(struct phy_devi
static void qca8084_remove(struct phy_device *phydev)
{

6
target/linux/qualcommbe/patches-6.18/0312-net-phy-qca808x-Add-QCA8084-SerDes-speed-config.patch
View File

@ -1,4 +1,4 @@
From 2f5b7e167d847a5b5b74a91f991d48635453c55f Mon Sep 17 00:00:00 2001
From c2d664e748ce7b96dbd07f79091527aaf1725165 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Mon, 23 Sep 2024 21:24:56 +0800
Subject: [PATCH] net: phy: qca808x: Add QCA8084 SerDes speed config
@ -214,7 +214,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
#endif /* _QCA8084_SERDES_H_ */
--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -976,6 +976,7 @@ static int qca8084_config_init(struct ph
@@ -997,6 +997,7 @@ static int qca8084_config_init(struct ph
static void qca8084_link_change_notify(struct phy_device *phydev)
{
@ -222,7 +222,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
int ret;
/* Assert the FIFO between PHY and MAC. */
@@ -1007,14 +1008,24 @@ static void qca8084_link_change_notify(s
@@ -1028,14 +1029,24 @@ static void qca8084_link_change_notify(s
}
}

2
target/linux/qualcommbe/patches-6.18/0313-dt-bindings-net-pcs-Add-Ethernet-PCS-for-Qualcomm-IP.patch
View File

@ -1,4 +1,4 @@
From 5f650721c4b232a14a1a3e25b686f2234faee961 Mon Sep 17 00:00:00 2001
From 0828bc67d0fee47eb1224a4fba93e9917f838ffc Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Fri, 7 Feb 2025 23:53:12 +0800
Subject: [PATCH] dt-bindings: net: pcs: Add Ethernet PCS for Qualcomm IPQ9574

6
target/linux/qualcommbe/patches-6.18/0314-net-pcs-Add-PCS-driver-for-Qualcomm-IPQ9574-SoC.patch
View File

@ -1,4 +1,4 @@
From e404519d9f3e5e7d661cb105d3766d87e37e4ef5 Mon Sep 17 00:00:00 2001
From c03b5a514b319c03a1883142694afa5deb69af6f Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Fri, 7 Feb 2025 23:53:13 +0800
Subject: [PATCH] net: pcs: Add PCS driver for Qualcomm IPQ9574 SoC
@ -40,8 +40,8 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+ to support different interface modes for MAC to PHY connections.
+
config PCS_RZN1_MIIC
tristate "Renesas RZ/N1 MII converter"
depends on OF && (ARCH_RZN1 || COMPILE_TEST)
tristate "Renesas RZ/N1, RZ/N2H, RZ/T2H MII converter"
depends on OF
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -7,5 +7,6 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.

4
target/linux/qualcommbe/patches-6.18/0315-net-pcs-qcom-ipq9574-Add-PCS-instantiation-and-phyli.patch
View File

@ -1,4 +1,4 @@
From 10b609ddbf4d369c80098efa39451ef3973759b5 Mon Sep 17 00:00:00 2001
From 58403accdc0c62dbba55befe607051a0ef68d64a Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Fri, 7 Feb 2025 23:53:14 +0800
Subject: [PATCH] net: pcs: qcom-ipq9574: Add PCS instantiation and phylink
@ -312,7 +312,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ clk_disable_unprepare(qpcs_mii->tx_clk);
+}
+
+static void ipq_pcs_get_state(struct phylink_pcs *pcs,
+static void ipq_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs);

2
target/linux/qualcommbe/patches-6.18/0316-net-pcs-qcom-ipq9574-Add-USXGMII-interface-mode-supp.patch
View File

@ -1,4 +1,4 @@
From 4923ca63214a4e6bbee1b3f8f6b9b79f0fd3a3be Mon Sep 17 00:00:00 2001
From bc30bc70975d985b05864d54d6c294022633cf8c Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Fri, 7 Feb 2025 23:53:15 +0800
Subject: [PATCH] net: pcs: qcom-ipq9574: Add USXGMII interface mode support

2
target/linux/qualcommbe/patches-6.18/0317-net-pcs-Add-10GBASER-interface-mode-support-to-IPQ-U.patch
View File

@ -1,4 +1,4 @@
From 432c2a2da1e0f4a8e2c0fea191361832a7f90f36 Mon Sep 17 00:00:00 2001
From 827dda24d66b1ecfaa4981b6fe505cedf0579e51 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Wed, 6 Mar 2024 17:40:52 +0800
Subject: [PATCH] net: pcs: Add 10GBASER interface mode support to IPQ UNIPHY

2
target/linux/qualcommbe/patches-6.18/0318-net-pcs-Add-2500BASEX-interface-mode-support-to-IPQ-.patch
View File

@ -1,4 +1,4 @@
From 0d3a93e3a5544daec59d8f10ac5ccab39849536e Mon Sep 17 00:00:00 2001
From aaa1ff298e5b354a9368bf27230e9f314d6a51eb Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Tue, 2 Apr 2024 18:28:42 +0800
Subject: [PATCH] net: pcs: Add 2500BASEX interface mode support to IPQ UNIPHY

2
target/linux/qualcommbe/patches-6.18/0319-net-pcs-Add-1000BASEX-interface-mode-support-to-IPQ-.patch
View File

@ -1,4 +1,4 @@
From d82953614a4f09dd7479e1d3904351ff85d1d088 Mon Sep 17 00:00:00 2001
From adc1625e7096b4da6802c6c8ef1f398f1670e856 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Tue, 9 Apr 2024 01:07:22 +0800
Subject: [PATCH] net: pcs: Add 1000BASEX interface mode support to IPQ UNIPHY

2
target/linux/qualcommbe/patches-6.18/0320-net-pcs-Add-10G_QXGMII-interface-mode-support-to-IPQ.patch
View File

@ -1,4 +1,4 @@
From fc26c6f6c69149ce87c88d6878ae929b2a138063 Mon Sep 17 00:00:00 2001
From 99115669f98a98bedaca1ec147440a205d3c90c1 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Mon, 15 Apr 2024 11:06:02 +0800
Subject: [PATCH] net: pcs: Add 10G_QXGMII interface mode support to IPQ UNIPHY

2
target/linux/qualcommbe/patches-6.18/0321-net-pcs-ipq-uniphy-control-MISC2-register-for-2.5G-s.patch
View File

@ -1,4 +1,4 @@
From 87da3bbd25eb0a17e2c698120528e76c26b326d0 Mon Sep 17 00:00:00 2001
From b5c662f1fd1f894a49e3f95582db5d48999e98ce Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Mon, 2 Jun 2025 17:18:13 +0300
Subject: [PATCH] net: pcs: ipq-uniphy: control MISC2 register for 2.5G support

2
target/linux/qualcommbe/patches-6.18/0322-net-pcs-ipq-uniphy-fix-USXGMII-link-up-failure.patch
View File

@ -1,4 +1,4 @@
From bedf56b46ae53c4abb21eebb3e1d5a7483926dda Mon Sep 17 00:00:00 2001
From 2812798881af3d170b32ef1f0d69ba5b9201f186 Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Mon, 2 Jun 2025 17:20:58 +0300
Subject: [PATCH] net: pcs: ipq-uniphy: fix USXGMII link-up failure

2
target/linux/qualcommbe/patches-6.18/0323-net-pcs-qcom-ipq9574-Update-IPQ9574-PCS-driver.patch
View File

@ -1,4 +1,4 @@
From b4e07a8a3ec3dc5f676238987556e2aff0b14028 Mon Sep 17 00:00:00 2001
From d7b52f91ca08479291817c5ac22991d032911e12 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Mon, 29 Jan 2024 11:39:36 +0800
Subject: [PATCH] net: pcs: qcom-ipq9574: Update IPQ9574 PCS driver

10
target/linux/qualcommbe/patches-6.18/0324-arm64-dts-qcom-ipq9574-add-PCS-uniphy-nodes.patch
View File

@ -1,4 +1,4 @@
From d6f184181b076cbb54f152994f5bc73ce524a67e Mon Sep 17 00:00:00 2001
From bfd4347fe459ab763044656cbf3227703d9c3b7b Mon Sep 17 00:00:00 2001
From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date: Sun, 11 May 2025 18:21:00 -0500
Subject: [PATCH] arm64: dts: qcom: ipq9574: add PCS uniphy nodes
@ -24,7 +24,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
@@ -1247,12 +1248,12 @@
@@ -1253,12 +1254,12 @@
<&cmn_pll NSS_1200MHZ_CLK>,
<&cmn_pll PPE_353MHZ_CLK>,
<&gcc GPLL0_OUT_AUX>,
@ -43,7 +43,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
<&gcc GCC_NSSCC_CLK>;
clock-names = "xo",
"nss_1200",
@@ -1269,6 +1270,93 @@
@@ -1275,6 +1276,93 @@
#reset-cells = <1>;
#interconnect-cells = <1>;
};
@ -93,7 +93,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ };
+ };
+
+ pcs1: ethernet-pcs@7a10000 {
+ pcs1: ethernet-uniphy@7a10000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq9574-pcs";
@ -105,7 +105,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ resets = <&gcc GCC_UNIPHY1_XPCS_RESET>;
+ #clock-cells = <1>;
+
+ pcs1_ch0: pcs-mii@0 {
+ pcs1_ch0: uniphy-ch@0 {
+ reg = <0>;
+ clocks = <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>,
+ <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>;

22
target/linux/qualcommbe/patches-6.18/0318-MAINTAINERS-Add-maintainer-for-Qualcomm-IPQ9574-PCS-.patch → target/linux/qualcommbe/patches-6.18/0325-MAINTAINERS-Add-maintainer-for-Qualcomm-PPE-driver.patch
View File

@ -1,19 +1,19 @@
From 34d10a4eb8fea32bb79e3012dc9d8bd2dffb0df3 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Fri, 7 Feb 2025 23:53:16 +0800
Subject: [PATCH] MAINTAINERS: Add maintainer for Qualcomm IPQ9574 PCS driver
From 2b80b27f2fb055b22fafe1ea143fa56b681cab4e Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Sun, 9 Feb 2025 22:29:48 +0800
Subject: [PATCH] MAINTAINERS: Add maintainer for Qualcomm PPE driver
Add maintainer for the Ethernet PCS driver supported for Qualcomm
IPQ9574 SoC.
Add maintainer entry for PPE (Packet Process Engine) driver
supported for Qualcomm IPQ SoCs.
Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19116,6 +19116,15 @@ S: Maintained
@@ -21233,6 +21233,15 @@ S: Maintained
F: Documentation/devicetree/bindings/regulator/vqmmc-ipq4019-regulator.yaml
F: drivers/regulator/vqmmc-ipq4019-regulator.c
@ -26,6 +26,6 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+F: include/dt-bindings/net/qcom,ipq9574-pcs.h
+F: include/linux/pcs/pcs-qcom-ipq9574.h
+
QUALCOMM NAND CONTROLLER DRIVER
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-mtd@lists.infradead.org
QUALCOMM IRIS VIDEO ACCELERATOR DRIVER
M: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
M: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>

8
target/linux/qualcommbe/patches-6.18/0326-net-ethernet-qualcomm-Add-PPE-scheduler-config.patch
View File

@ -1,4 +1,4 @@
From 93cf3297818ee61607f0a8d1d34e4fb7fcde3cdf Mon Sep 17 00:00:00 2001
From cd111b91e3cc1d6955dd116bec697f3d909fb419 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Tue, 26 Dec 2023 20:18:09 +0800
Subject: [PATCH] net: ethernet: qualcomm: Add PPE scheduler config
@ -23,7 +23,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
@@ -864,6 +864,51 @@ static int ppe_scheduler_l0_queue_map_se
@@ -889,6 +889,51 @@ static int ppe_scheduler_l0_queue_map_se
val);
}
@ -75,7 +75,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Set the PPE flow level scheduler configuration. */
static int ppe_scheduler_l1_queue_map_set(struct ppe_device *ppe_dev,
int node_id, int port,
@@ -916,6 +961,50 @@ static int ppe_scheduler_l1_queue_map_se
@@ -941,6 +986,50 @@ static int ppe_scheduler_l1_queue_map_se
return regmap_update_bits(ppe_dev->regmap, reg, PPE_L1_COMP_CFG_TBL_NODE_METER_LEN, val);
}
@ -126,7 +126,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/**
* ppe_queue_scheduler_set - Configure scheduler for PPE hardware queue
* @ppe_dev: PPE device
@@ -942,6 +1031,58 @@ int ppe_queue_scheduler_set(struct ppe_d
@@ -967,6 +1056,58 @@ int ppe_queue_scheduler_set(struct ppe_d
}
/**

44
target/linux/qualcommbe/patches-6.18/0327-net-ethernet-qualcomm-Add-phylink-support-for-PPE-MA.patch
View File

@ -1,4 +1,4 @@
From dbb3711ab25ea410ad5286b2f39dccd954cda225 Mon Sep 17 00:00:00 2001
From 54bae579f3e6bea90322412a473e00d6815567de Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Thu, 29 Feb 2024 16:59:53 +0800
Subject: [PATCH] net: ethernet: qualcomm: Add phylink support for PPE MAC
@ -8,6 +8,9 @@ Add MAC initialization and phylink functions for PPE MAC ports.
Change-Id: I39dcba671732392bcfa2e734473fd083989bfbec
Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
Alex G: Use ipq_pcs_get/put() instead of ipq_unipcs_create/destroy()
Drop "port_" prefix from devicetree clock and reset names
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/net/ethernet/qualcomm/Kconfig | 3 +
drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +-
@ -15,16 +18,16 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
drivers/net/ethernet/qualcomm/ppe/ppe.h | 2 +
drivers/net/ethernet/qualcomm/ppe/ppe_port.c | 728 +++++++++++++++++++
drivers/net/ethernet/qualcomm/ppe/ppe_port.h | 76 ++
drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 124 ++++
7 files changed, 943 insertions(+), 1 deletion(-)
drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 126 ++++
7 files changed, 945 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_port.c
create mode 100644 drivers/net/ethernet/qualcomm/ppe/ppe_port.h
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
@@ -66,6 +66,9 @@ config QCOM_PPE
depends on HAS_IOMEM && OF
depends on COMMON_CLK
@@ -65,6 +65,9 @@ config QCOM_PPE
depends on COMMON_CLK && HAS_IOMEM && OF
depends on ARCH_QCOM || COMPILE_TEST
select REGMAP_MMIO
+ select PHYLINK
+ select PCS_QCOM_IPQ_UNIPHY
@ -50,7 +53,7 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
#define PPE_PORT_MAX 8
#define PPE_CLK_RATE 353000000
@@ -200,6 +201,11 @@ static int qcom_ppe_probe(struct platfor
@@ -205,6 +206,11 @@ static int qcom_ppe_probe(struct platfor
if (ret)
return dev_err_probe(dev, ret, "PPE HW config failed\n");
@ -62,7 +65,7 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
ppe_debugfs_setup(ppe_dev);
platform_set_drvdata(pdev, ppe_dev);
@@ -212,6 +218,9 @@ static void qcom_ppe_remove(struct platf
@@ -217,6 +223,9 @@ static void qcom_ppe_remove(struct platf
ppe_dev = platform_get_drvdata(pdev);
ppe_debugfs_teardown(ppe_dev);
@ -120,9 +123,9 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+
+/* PPE port clock and reset name */
+static const char * const ppe_port_clk_rst_name[] = {
+ [PPE_PORT_CLK_RST_MAC] = "port_mac",
+ [PPE_PORT_CLK_RST_RX] = "port_rx",
+ [PPE_PORT_CLK_RST_TX] = "port_tx",
+ [PPE_PORT_CLK_RST_MAC] = "mac",
+ [PPE_PORT_CLK_RST_RX] = "rx",
+ [PPE_PORT_CLK_RST_TX] = "tx",
+};
+
+/* PPE port and MAC reset */
@ -920,11 +923,20 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
/* PPE scheduler configurations for buffer manager block. */
#define PPE_BM_SCH_CTRL_ADDR 0xb000
#define PPE_BM_SCH_CTRL_INC 4
@@ -556,4 +567,117 @@
#define PPE_ENQ_OPR_TBL_ENTRIES 300
@@ -26,6 +37,9 @@
#define PPE_DROP_STAT_TBL_ENTRIES 30
#define PPE_DROP_STAT_TBL_INC 0x10
+#define PPE_EPE_DBG_IN_CNT_ADDR 0x26054
+#define PPE_EPE_DBG_OUT_CNT_ADDR 0x26070
+
/* Egress VLAN counters. */
#define PPE_EG_VSI_COUNTER_TBL_ADDR 0x41000
#define PPE_EG_VSI_COUNTER_TBL_ENTRIES 64
@@ -554,6 +568,118 @@
#define PPE_ENQ_OPR_TBL_INC 0x10
#define PPE_ENQ_OPR_TBL_ENQ_DISABLE BIT(0)
+
+/* PPE GMAC and XGMAC register base address */
+#define PPE_PORT_GMAC_ADDR(x) (0x001000 + ((x) - 1) * 0x200)
+#define PPE_PORT_XGMAC_ADDR(x) (0x500000 + ((x) - 1) * 0x4000)
@ -1037,4 +1049,6 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+#define XGMAC_MCF BIT(3)
+#define XGMAC_CNTRST BIT(0)
+
#endif
/* Unicast drop count includes the possible drops with WRED for the green,
* yellow and red categories.
*/

12
target/linux/qualcommbe/patches-6.18/0328-net-ethernet-qualcomm-Add-PPE-port-MAC-MIB-statistic.patch
View File

@ -1,4 +1,4 @@
From dbcc0d01241a1353d8e11e764cf7fcd390ae3f1f Mon Sep 17 00:00:00 2001
From 9ecd759aafd85b92ac2865748ea62af8211bce74 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Thu, 29 Feb 2024 20:16:14 +0800
Subject: [PATCH] net: ethernet: qualcomm: Add PPE port MAC MIB statistics
@ -140,9 +140,9 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+
/* PPE port clock and reset name */
static const char * const ppe_port_clk_rst_name[] = {
[PPE_PORT_CLK_RST_MAC] = "port_mac",
[PPE_PORT_CLK_RST_MAC] = "mac",
@@ -30,6 +146,322 @@ static const char * const ppe_port_clk_r
[PPE_PORT_CLK_RST_TX] = "port_tx",
[PPE_PORT_CLK_RST_TX] = "tx",
};
+/* PPE GMAC MIB statistics description information */
@ -617,7 +617,7 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
/* XGMAC TX configuration register */
#define XGMAC_TX_CONFIG_ADDR 0x0
#define XGMAC_SPEED_M GENMASK(31, 29)
@@ -680,4 +722,53 @@
@@ -680,6 +722,55 @@
#define XGMAC_MCF BIT(3)
#define XGMAC_CNTRST BIT(0)
@ -670,4 +670,6 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+#define XGMAC_RXDISCARD_GB_ADDR 0x9AC
+#define XGMAC_RXDISCARDBYTE_GB_ADDR 0x9B4
+
#endif
/* Unicast drop count includes the possible drops with WRED for the green,
* yellow and red categories.
*/

2
target/linux/qualcommbe/patches-6.18/0329-net-ethernet-qualcomm-Add-PPE-port-MAC-address-and-E.patch
View File

@ -1,4 +1,4 @@
From 55fbbc8ef90df27a16bca1613a793a578b79a384 Mon Sep 17 00:00:00 2001
From 15e70eb335652f61fdf1b645736f7782b88368c0 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Fri, 1 Mar 2024 13:36:26 +0800
Subject: [PATCH] net: ethernet: qualcomm: Add PPE port MAC address and EEE

2
target/linux/qualcommbe/patches-6.18/0330-net-ethernet-qualcomm-Add-API-to-configure-PPE-port-.patch
View File

@ -1,4 +1,4 @@
From 3981aeae5dd43dea94a0ec10f0b2977ebd102560 Mon Sep 17 00:00:00 2001
From e2f7ca2d156a194b20af7532c494360013c1603e Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Tue, 5 Mar 2024 16:42:56 +0800
Subject: [PATCH] net: ethernet: qualcomm: Add API to configure PPE port max

44
target/linux/qualcommbe/patches-6.18/0331-net-ethernet-qualcomm-Add-EDMA-support-for-QCOM-IPQ9.patch
View File

@ -1,4 +1,4 @@
From 00d4f3cb4f5d1e6924151a4551f06b6a82bf0146 Mon Sep 17 00:00:00 2001
From 56df33745951d0a8f57e697f6d38fd69760ce2ee Mon Sep 17 00:00:00 2001
From: Pavithra R <quic_pavir@quicinc.com>
Date: Wed, 28 Feb 2024 11:25:15 +0530
Subject: [PATCH] net: ethernet: qualcomm: Add EDMA support for QCOM IPQ9574
@ -15,14 +15,15 @@ Alex G: use "ppe_config.h" header instead of "ppe_api.h"
add missing definitions and functions from ppe_api:
- enum ppe_queue_class_type {}
- ppe_edma_queue_offset_config()
use new devicetree prpoerty names as suggested by Luo Jie
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/net/ethernet/qualcomm/ppe/Makefile | 3 +
drivers/net/ethernet/qualcomm/ppe/edma.c | 480 +++++++++++++++++++
drivers/net/ethernet/qualcomm/ppe/edma.c | 481 +++++++++++++++++++
drivers/net/ethernet/qualcomm/ppe/edma.h | 113 +++++
drivers/net/ethernet/qualcomm/ppe/ppe.c | 10 +-
drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 253 ++++++++++
5 files changed, 858 insertions(+), 1 deletion(-)
5 files changed, 859 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma.c
create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma.h
@ -37,7 +38,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+qcom-ppe-objs += edma.o
--- /dev/null
+++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
@@ -0,0 +1,480 @@
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: GPL-2.0-only
+ /* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
@ -61,6 +62,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+#include "ppe_regs.h"
+
+#define EDMA_IRQ_NAME_SIZE 32
+#define EDMA_NODE_NAME "ethernet-dma"
+
+/* Global EDMA context. */
+struct edma_context *edma_ctx;
@ -70,14 +72,14 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ 0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7};
+
+enum edma_clk_id {
+ EDMA_CLK,
+ EDMA_CFG_CLK,
+ EDMA_SYS_CLK,
+ EDMA_APB_CLK,
+ EDMA_CLK_MAX
+};
+
+static const char * const clock_name[EDMA_CLK_MAX] = {
+ [EDMA_CLK] = "edma",
+ [EDMA_CFG_CLK] = "edma-cfg",
+ [EDMA_SYS_CLK] = "sys",
+ [EDMA_APB_CLK] = "apb",
+};
+
+/* Rx Fill ring info for IPQ9574. */
@ -126,7 +128,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ struct clk *clk = NULL;
+ int ret;
+
+ edma_np = of_get_child_by_name(dev->of_node, "edma");
+ edma_np = of_get_child_by_name(dev->of_node, EDMA_NODE_NAME);
+
+ clk = devm_get_clk_from_child(dev, edma_np, id);
+ if (IS_ERR(clk)) {
@ -165,12 +167,12 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+
+ ppe_rate = ppe_dev->clk_rate;
+
+ ret = edma_clock_set_and_enable(dev, clock_name[EDMA_CLK],
+ ret = edma_clock_set_and_enable(dev, clock_name[EDMA_SYS_CLK],
+ ppe_rate);
+ if (ret)
+ return ret;
+
+ ret = edma_clock_set_and_enable(dev, clock_name[EDMA_CFG_CLK],
+ ret = edma_clock_set_and_enable(dev, clock_name[EDMA_APB_CLK],
+ ppe_rate);
+ if (ret)
+ return ret;
@ -231,7 +233,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ u32 i;
+
+ pdev = to_platform_device(dev);
+ edma_np = of_get_child_by_name(dev->of_node, "edma");
+ edma_np = of_get_child_by_name(dev->of_node, EDMA_NODE_NAME);
+ edma_ctx->intr_info.intr_txcmpl = kzalloc((sizeof(*edma_ctx->intr_info.intr_txcmpl) *
+ txcmpl->num_rings), GFP_KERNEL);
+ if (!edma_ctx->intr_info.intr_txcmpl) {
@ -241,7 +243,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+
+ /* Get TXCMPL rings IRQ numbers. */
+ for (i = 0; i < txcmpl->num_rings; i++) {
+ snprintf(edma_irq_name, sizeof(edma_irq_name), "edma_txcmpl_%d",
+ snprintf(edma_irq_name, sizeof(edma_irq_name), "txcmpl_%d",
+ txcmpl->ring_start + i);
+ edma_ctx->intr_info.intr_txcmpl[i] = of_irq_get_byname(edma_np, edma_irq_name);
+ if (edma_ctx->intr_info.intr_txcmpl[i] < 0) {
@ -266,7 +268,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+
+ /* Get RXDESC rings IRQ numbers. */
+ for (i = 0; i < rx->num_rings; i++) {
+ snprintf(edma_irq_name, sizeof(edma_irq_name), "edma_rxdesc_%d",
+ snprintf(edma_irq_name, sizeof(edma_irq_name), "rxdesc_%d",
+ rx->ring_start + i);
+ edma_ctx->intr_info.intr_rx[i] = of_irq_get_byname(edma_np, edma_irq_name);
+ if (edma_ctx->intr_info.intr_rx[i] < 0) {
@ -283,7 +285,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ }
+
+ /* Get misc IRQ number. */
+ edma_ctx->intr_info.intr_misc = of_irq_get_byname(edma_np, "edma_misc");
+ edma_ctx->intr_info.intr_misc = of_irq_get_byname(edma_np, "misc");
+ if (edma_ctx->intr_info.intr_misc < 0) {
+ dev_err(dev, "%s: misc_intr irq get failed\n", edma_np->name);
+ of_node_put(edma_np);
@ -311,7 +313,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ int ret;
+
+ /* Count and parse reset names from DTSI. */
+ edma_np = of_get_child_by_name(dev->of_node, "edma");
+ edma_np = of_get_child_by_name(dev->of_node, EDMA_NODE_NAME);
+ count = of_property_count_strings(edma_np, "reset-names");
+ if (count < 0) {
+ dev_err(dev, "EDMA reset entry not found\n");
@ -644,7 +646,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
#include "ppe.h"
#include "ppe_config.h"
#include "ppe_debugfs.h"
@@ -201,10 +202,16 @@ static int qcom_ppe_probe(struct platfor
@@ -206,10 +207,16 @@ static int qcom_ppe_probe(struct platfor
if (ret)
return dev_err_probe(dev, ret, "PPE HW config failed\n");
@ -662,7 +664,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
ppe_debugfs_setup(ppe_dev);
platform_set_drvdata(pdev, ppe_dev);
@@ -219,6 +226,7 @@ static void qcom_ppe_remove(struct platf
@@ -224,6 +231,7 @@ static void qcom_ppe_remove(struct platf
ppe_dev = platform_get_drvdata(pdev);
ppe_debugfs_teardown(ppe_dev);
ppe_port_mac_deinit(ppe_dev);
@ -672,7 +674,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
}
--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
@@ -800,4 +800,257 @@
@@ -800,6 +800,259 @@
#define XGMAC_RXDISCARD_GB_ADDR 0x9AC
#define XGMAC_RXDISCARDBYTE_GB_ADDR 0x9B4
@ -929,4 +931,6 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+/* EDMA rxdesc2fill map */
+#define EDMA_RXDESC2FILL_MAP_RXDESC_MASK 0x7
+
#endif
/* Unicast drop count includes the possible drops with WRED for the green,
* yellow and red categories.
*/

2
target/linux/qualcommbe/patches-6.18/0332-net-ethernet-qualcomm-Add-netdevice-support-for-QCOM.patch
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@ -1,4 +1,4 @@
From 5dc80c468c668d855d76b323f09bbadb95cc3147 Mon Sep 17 00:00:00 2001
From 9556d8b3d5914e7ed7e5e0f59945f9c3ab2655a0 Mon Sep 17 00:00:00 2001
From: Suruchi Agarwal <quic_suruchia@quicinc.com>
Date: Thu, 21 Mar 2024 16:14:46 -0700
Subject: [PATCH] net: ethernet: qualcomm: Add netdevice support for QCOM

26
target/linux/qualcommbe/patches-6.18/0333-net-ethernet-qualcomm-Add-Rx-Ethernet-DMA-support.patch
View File

@ -1,4 +1,4 @@
From b5c8c5d3888328321e8be1db50b75dff8f514e51 Mon Sep 17 00:00:00 2001
From 6b1bc69249055b08cbe3fae9530288246af52e73 Mon Sep 17 00:00:00 2001
From: Suruchi Agarwal <quic_suruchia@quicinc.com>
Date: Thu, 21 Mar 2024 16:21:19 -0700
Subject: [PATCH] net: ethernet: qualcomm: Add Rx Ethernet DMA support
@ -13,6 +13,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
Alex G: add missing functions that were previously in ppe_api.c:
- ppe_edma_queue_resource_get()
- ppe_edma_ring_to_queues_config()
Use rxdesc_* for IRQ name instead of edma_rxdesc_*
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +-
@ -40,7 +41,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+qcom-ppe-objs += edma.o edma_cfg_rx.o edma_port.o edma_rx.o
--- a/drivers/net/ethernet/qualcomm/ppe/edma.c
+++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
@@ -18,12 +18,23 @@
@@ -18,6 +18,7 @@
#include <linux/reset.h>
#include "edma.h"
@ -48,6 +49,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
#include "ppe_regs.h"
#define EDMA_IRQ_NAME_SIZE 32
@@ -25,6 +26,16 @@
/* Global EDMA context. */
struct edma_context *edma_ctx;
@ -64,7 +66,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Priority to multi-queue mapping. */
static u8 edma_pri_map[PPE_QUEUE_INTER_PRI_NUM] = {
@@ -178,6 +189,59 @@ static int edma_configure_ucast_prio_map
@@ -179,6 +190,59 @@ static int edma_configure_ucast_prio_map
return ret;
}
@ -89,7 +91,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ goto rxdesc_irq_name_alloc_fail;
+ }
+
+ snprintf(edma_rxdesc_irq_name[i], 20, "edma_rxdesc_%d",
+ snprintf(edma_rxdesc_irq_name[i], 20, "rxdesc_%d",
+ rx->ring_start + i);
+
+ irq_set_status_flags(edma_ctx->intr_info.intr_rx[i], IRQ_DISABLE_UNLAZY);
@ -124,7 +126,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
static int edma_irq_init(void)
{
struct edma_hw_info *hw_info = edma_ctx->hw_info;
@@ -260,6 +324,16 @@ static int edma_irq_init(void)
@@ -261,6 +325,16 @@ static int edma_irq_init(void)
return 0;
}
@ -141,7 +143,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
static int edma_hw_reset(void)
{
struct ppe_device *ppe_dev = edma_ctx->ppe_dev;
@@ -343,6 +417,40 @@ static int edma_hw_configure(void)
@@ -344,6 +418,40 @@ static int edma_hw_configure(void)
if (!edma_ctx->netdev_arr)
return -ENOMEM;
@ -182,7 +184,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Configure DMA request priority, DMA read burst length,
* and AXI write size.
*/
@@ -376,6 +484,10 @@ static int edma_hw_configure(void)
@@ -377,6 +485,10 @@ static int edma_hw_configure(void)
data |= EDMA_MISC_TX_TIMEOUT_MASK;
edma_ctx->intr_info.intr_mask_misc = data;
@ -193,7 +195,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Global EDMA enable and padding enable. */
data = EDMA_PORT_PAD_EN | EDMA_PORT_EDMA_EN;
@@ -389,11 +501,32 @@ static int edma_hw_configure(void)
@@ -390,11 +502,32 @@ static int edma_hw_configure(void)
if (ret) {
pr_err("Failed to initialize unicast priority map table: %d\n",
ret);
@ -228,7 +230,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
}
/**
@@ -404,8 +537,31 @@ static int edma_hw_configure(void)
@@ -405,8 +538,31 @@ static int edma_hw_configure(void)
*/
void edma_destroy(struct ppe_device *ppe_dev)
{
@ -260,7 +262,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
kfree(edma_ctx->netdev_arr);
}
@@ -428,6 +584,7 @@ int edma_setup(struct ppe_device *ppe_de
@@ -429,6 +585,7 @@ int edma_setup(struct ppe_device *ppe_de
edma_ctx->hw_info = &ipq9574_hw_info;
edma_ctx->ppe_dev = ppe_dev;
@ -268,7 +270,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Configure the EDMA common clocks. */
ret = edma_clock_init();
@@ -450,6 +607,16 @@ int edma_setup(struct ppe_device *ppe_de
@@ -451,6 +608,16 @@ int edma_setup(struct ppe_device *ppe_de
return ret;
}
@ -285,7 +287,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
dev_info(dev, "EDMA configuration successful\n");
return 0;
@@ -478,3 +645,46 @@ int ppe_edma_queue_offset_config(struct
@@ -479,3 +646,46 @@ int ppe_edma_queue_offset_config(struct
return ppe_queue_ucast_offset_hash_set(ppe_dev, 0,
index, queue_offset);
}

28
target/linux/qualcommbe/patches-6.18/0334-net-ethernet-qualcomm-Add-Tx-Ethernet-DMA-support.patch
View File

@ -1,4 +1,4 @@
From 339d3a5365f150a78ed405684e379fee3acdbe90 Mon Sep 17 00:00:00 2001
From c5b1699a62ce8df5680db0bad0d748fe4018f3b0 Mon Sep 17 00:00:00 2001
From: Suruchi Agarwal <quic_suruchia@quicinc.com>
Date: Thu, 21 Mar 2024 16:26:29 -0700
Subject: [PATCH] net: ethernet: qualcomm: Add Tx Ethernet DMA support
@ -10,6 +10,8 @@ Change-Id: Idfb0e1fe5ac494d614097d6c97dd15d63bbce8e6
Co-developed-by: Pavithra R <quic_pavir@quicinc.com>
Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
Alex G: Use txcompl_* for IRQ name instead of edma_txcompl_*
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +-
drivers/net/ethernet/qualcomm/ppe/edma.c | 97 ++-
@ -44,7 +46,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
#include "edma_cfg_rx.h"
#include "ppe_regs.h"
@@ -25,6 +26,7 @@
@@ -26,6 +27,7 @@
/* Global EDMA context. */
struct edma_context *edma_ctx;
@ -52,7 +54,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
static char **edma_rxdesc_irq_name;
/* Module params. */
@@ -192,22 +194,59 @@ static int edma_configure_ucast_prio_map
@@ -193,22 +195,59 @@ static int edma_configure_ucast_prio_map
static int edma_irq_register(void)
{
struct edma_hw_info *hw_info = edma_ctx->hw_info;
@ -74,7 +76,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
+ goto txcmpl_ring_irq_name_alloc_fail;
+ }
+
+ snprintf(edma_txcmpl_irq_name[i], EDMA_IRQ_NAME_SIZE, "edma_txcmpl_%d",
+ snprintf(edma_txcmpl_irq_name[i], EDMA_IRQ_NAME_SIZE, "txcmpl_%d",
+ txcmpl->ring_start + i);
+
+ irq_set_status_flags(edma_ctx->intr_info.intr_txcmpl[i], IRQ_DISABLE_UNLAZY);
@ -114,8 +116,8 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
+ goto rxdesc_ring_irq_name_alloc_fail;
}
snprintf(edma_rxdesc_irq_name[i], 20, "edma_rxdesc_%d",
@@ -236,8 +275,19 @@ static int edma_irq_register(void)
snprintf(edma_rxdesc_irq_name[i], 20, "rxdesc_%d",
@@ -237,8 +276,19 @@ static int edma_irq_register(void)
rx_desc_ring_intr_req_fail:
for (i = 0; i < rx->num_rings; i++)
kfree(edma_rxdesc_irq_name[i]);
@ -136,7 +138,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
return ret;
}
@@ -326,12 +376,22 @@ static int edma_irq_init(void)
@@ -327,12 +377,22 @@ static int edma_irq_init(void)
static int edma_alloc_rings(void)
{
@ -160,7 +162,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
}
static int edma_hw_reset(void)
@@ -389,7 +449,7 @@ static int edma_hw_configure(void)
@@ -390,7 +450,7 @@ static int edma_hw_configure(void)
struct edma_hw_info *hw_info = edma_ctx->hw_info;
struct ppe_device *ppe_dev = edma_ctx->ppe_dev;
struct regmap *regmap = ppe_dev->regmap;
@ -169,7 +171,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
int ret;
reg = EDMA_BASE_OFFSET + EDMA_REG_MAS_CTRL_ADDR;
@@ -439,11 +499,17 @@ static int edma_hw_configure(void)
@@ -440,11 +500,17 @@ static int edma_hw_configure(void)
}
/* Disable interrupts. */
@ -187,7 +189,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
ret = edma_cfg_rx_rings();
if (ret) {
@@ -520,6 +586,7 @@ configure_ucast_prio_map_tbl_failed:
@@ -521,6 +587,7 @@ configure_ucast_prio_map_tbl_failed:
edma_cfg_rx_napi_delete();
edma_cfg_rx_rings_disable();
edma_cfg_rx_rings_failed:
@ -195,7 +197,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
edma_cfg_rx_rings_cleanup();
edma_alloc_rings_failed:
free_netdev(edma_ctx->dummy_dev);
@@ -538,13 +605,27 @@ dummy_dev_alloc_failed:
@@ -539,13 +606,27 @@ dummy_dev_alloc_failed:
void edma_destroy(struct ppe_device *ppe_dev)
{
struct edma_hw_info *hw_info = edma_ctx->hw_info;
@ -224,7 +226,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
for (i = 0; i < rx->num_rings; i++) {
synchronize_irq(edma_ctx->intr_info.intr_rx[i]);
free_irq(edma_ctx->intr_info.intr_rx[i],
@@ -560,6 +641,7 @@ void edma_destroy(struct ppe_device *ppe
@@ -561,6 +642,7 @@ void edma_destroy(struct ppe_device *ppe
edma_cfg_rx_napi_delete();
edma_cfg_rx_rings_disable();
edma_cfg_rx_rings_cleanup();
@ -232,7 +234,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
free_netdev(edma_ctx->dummy_dev);
kfree(edma_ctx->netdev_arr);
@@ -585,6 +667,7 @@ int edma_setup(struct ppe_device *ppe_de
@@ -586,6 +668,7 @@ int edma_setup(struct ppe_device *ppe_de
edma_ctx->hw_info = &ipq9574_hw_info;
edma_ctx->ppe_dev = ppe_dev;
edma_ctx->rx_buf_size = rx_buff_size;

60
target/linux/qualcommbe/patches-6.18/0335-net-ethernet-qualcomm-Add-miscellaneous-error-interr.patch
View File

@ -1,4 +1,4 @@
From 8a924457c0b71acee96c8f78ef386e2a354a2aca Mon Sep 17 00:00:00 2001
From 3a189759d41467c33ab2353da24ce42bc630afad Mon Sep 17 00:00:00 2001
From: Suruchi Agarwal <quic_suruchia@quicinc.com>
Date: Thu, 21 Mar 2024 16:31:04 -0700
Subject: [PATCH] net: ethernet: qualcomm: Add miscellaneous error interrupts
@ -11,13 +11,15 @@ Change-Id: I7da8b978a7e93947b03a45269a81b401f35da31c
Co-developed-by: Pavithra R <quic_pavir@quicinc.com>
Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
Alex G: Use "misc" for IRQ name instead of "edma_misc"
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
drivers/net/ethernet/qualcomm/ppe/Makefile | 2 +-
drivers/net/ethernet/qualcomm/ppe/edma.c | 162 ++++++++
drivers/net/ethernet/qualcomm/ppe/edma.h | 30 ++
.../net/ethernet/qualcomm/ppe/edma_debugfs.c | 370 ++++++++++++++++++
.../net/ethernet/qualcomm/ppe/ppe_debugfs.c | 17 +
5 files changed, 580 insertions(+), 1 deletion(-)
.../net/ethernet/qualcomm/ppe/ppe_debugfs.c | 15 +-
5 files changed, 577 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/qualcomm/ppe/edma_debugfs.c
--- a/drivers/net/ethernet/qualcomm/ppe/Makefile
@ -30,7 +32,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
+qcom-ppe-objs += edma.o edma_cfg_rx.o edma_cfg_tx.o edma_debugfs.o edma_port.o edma_rx.o edma_tx.o
--- a/drivers/net/ethernet/qualcomm/ppe/edma.c
+++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
@@ -152,6 +152,42 @@ static int edma_clock_init(void)
@@ -153,6 +153,42 @@ static int edma_clock_init(void)
}
/**
@ -73,7 +75,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
* edma_configure_ucast_prio_map_tbl - Configure unicast priority map table.
*
* Map int_priority values to priority class and initialize
@@ -191,11 +227,113 @@ static int edma_configure_ucast_prio_map
@@ -192,11 +228,113 @@ static int edma_configure_ucast_prio_map
return ret;
}
@ -187,13 +189,13 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
int ret;
u32 i;
@@ -270,8 +408,25 @@ static int edma_irq_register(void)
@@ -271,8 +409,25 @@ static int edma_irq_register(void)
edma_rxdesc_irq_name[i]);
}
+ /* Request Misc IRQ */
+ ret = request_irq(edma_ctx->intr_info.intr_misc, edma_misc_handle_irq,
+ IRQF_SHARED, "edma_misc",
+ IRQF_SHARED, "misc",
+ (void *)dev);
+ if (ret) {
+ pr_err("MISC IRQ:%d request failed\n",
@ -213,7 +215,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
rx_desc_ring_intr_req_fail:
for (i = 0; i < rx->num_rings; i++)
kfree(edma_rxdesc_irq_name[i]);
@@ -503,6 +658,7 @@ static int edma_hw_configure(void)
@@ -504,6 +659,7 @@ static int edma_hw_configure(void)
edma_cfg_tx_disable_interrupts(i);
edma_cfg_rx_disable_interrupts();
@ -221,7 +223,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
edma_cfg_rx_rings_disable();
@@ -614,6 +770,7 @@ void edma_destroy(struct ppe_device *ppe
@@ -615,6 +771,7 @@ void edma_destroy(struct ppe_device *ppe
edma_cfg_tx_disable_interrupts(i);
edma_cfg_rx_disable_interrupts();
@ -229,7 +231,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
/* Free IRQ for TXCMPL rings. */
for (i = 0; i < txcmpl->num_rings; i++) {
@@ -634,6 +791,10 @@ void edma_destroy(struct ppe_device *ppe
@@ -635,6 +792,10 @@ void edma_destroy(struct ppe_device *ppe
}
kfree(edma_rxdesc_irq_name);
@ -240,7 +242,7 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
kfree(edma_ctx->intr_info.intr_rx);
kfree(edma_ctx->intr_info.intr_txcmpl);
@@ -699,6 +860,7 @@ int edma_setup(struct ppe_device *ppe_de
@@ -700,6 +861,7 @@ int edma_setup(struct ppe_device *ppe_de
}
edma_cfg_rx_enable_interrupts();
@ -685,10 +687,10 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
+}
--- a/drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c
+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_debugfs.c
@@ -7,9 +7,11 @@
#include <linux/bitfield.h>
@@ -9,9 +9,11 @@
#include <linux/debugfs.h>
#include <linux/dev_printk.h>
#include <linux/device.h>
+#include <linux/netdevice.h>
#include <linux/regmap.h>
#include <linux/seq_file.h>
@ -697,23 +699,28 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
#include "ppe.h"
#include "ppe_config.h"
#include "ppe_debugfs.h"
@@ -678,15 +680,30 @@ static const struct file_operations ppe_
@@ -820,11 +822,14 @@ DEFINE_SHOW_STORE_ATTRIBUTE(ppe_packet_c
void ppe_debugfs_setup(struct ppe_device *ppe_dev)
{
struct ppe_debugfs_entry *entry;
+ int ret;
+
int i;
ppe_dev->debugfs_root = debugfs_create_dir("ppe", NULL);
debugfs_create_file("packet_counters", 0444,
ppe_dev->debugfs_root,
ppe_dev,
&ppe_debugfs_packet_counter_fops);
+
+ if (!ppe_dev->debugfs_root) {
- if (IS_ERR(ppe_dev->debugfs_root))
+ if (IS_ERR(ppe_dev->debugfs_root)) {
+ dev_err(ppe_dev->dev, "Error in PPE debugfs setup\n");
+ return;
return;
+ }
for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) {
entry = devm_kzalloc(ppe_dev->dev, sizeof(*entry), GFP_KERNEL);
@@ -838,6 +843,14 @@ void ppe_debugfs_setup(struct ppe_device
ppe_dev->debugfs_root, entry,
&ppe_packet_counter_fops);
}
+
+ /* TODO: Do we have to be so agressive and remove __all__ debugfs entries? */
+ ret = edma_debugfs_setup(ppe_dev);
+ if (ret) {
+ dev_err(ppe_dev->dev, "Error in EDMA debugfs setup API. ret: %d\n", ret);
@ -723,8 +730,3 @@ Signed-off-by: Suruchi Agarwal <quic_suruchia@quicinc.com>
}
void ppe_debugfs_teardown(struct ppe_device *ppe_dev)
{
+ edma_debugfs_teardown();
debugfs_remove_recursive(ppe_dev->debugfs_root);
ppe_dev->debugfs_root = NULL;
}

30
target/linux/qualcommbe/patches-6.18/0336-MAINTAINERS-Add-maintainer-for-Qualcomm-PPE-driver.patch
View File

@ -1,30 +0,0 @@
From 28098c348414fa97531449d4e27ba1587e67c2d9 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Sun, 9 Feb 2025 22:29:48 +0800
Subject: [PATCH] MAINTAINERS: Add maintainer for Qualcomm PPE driver
Add maintainer entry for PPE (Packet Process Engine) driver
supported for Qualcomm IPQ SoCs.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19133,6 +19133,14 @@ S: Maintained
F: Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
F: drivers/mtd/nand/raw/qcom_nandc.c
+QUALCOMM PPE DRIVER
+M: Luo Jie <quic_luoj@quicinc.com>
+L: netdev@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
+F: Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst
+F: drivers/net/ethernet/qualcomm/ppe/
+
QUALCOMM QSEECOM DRIVER
M: Maximilian Luz <luzmaximilian@gmail.com>
L: linux-arm-msm@vger.kernel.org

2
target/linux/qualcommbe/patches-6.18/0336-net-ethernet-qualcomm-Add-ethtool-support-for-EDMA.patch
View File

@ -1,4 +1,4 @@
From bd61a680fb657eb65272225f18c93fe338c700da Mon Sep 17 00:00:00 2001
From 033ce0e809a31c25ce96eafce0e84214735ac56c Mon Sep 17 00:00:00 2001
From: Pavithra R <quic_pavir@quicinc.com>
Date: Thu, 30 May 2024 20:46:36 +0530
Subject: [PATCH] net: ethernet: qualcomm: Add ethtool support for EDMA

6
target/linux/qualcommbe/patches-6.18/0337-net-ethernet-qualcomm-Add-module-parameters-for-driv.patch
View File

@ -1,4 +1,4 @@
From 2ecec7e47e269e05cdd393c34aae51d4866070c6 Mon Sep 17 00:00:00 2001
From eda6fa4f6044cc55dcb4fd6ea384bf2680602667 Mon Sep 17 00:00:00 2001
From: Pavithra R <quic_pavir@quicinc.com>
Date: Tue, 11 Jun 2024 00:00:46 +0530
Subject: [PATCH] net: ethernet: qualcomm: Add module parameters for driver
@ -21,7 +21,7 @@ Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
--- a/drivers/net/ethernet/qualcomm/ppe/edma.c
+++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
@@ -38,6 +38,38 @@ static int rx_buff_size;
@@ -39,6 +39,38 @@ static int rx_buff_size;
module_param(rx_buff_size, int, 0640);
MODULE_PARM_DESC(rx_buff_size, "Rx Buffer size for Jumbo MRU value (default:0)");
@ -60,7 +60,7 @@ Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
/* Priority to multi-queue mapping. */
static u8 edma_pri_map[PPE_QUEUE_INTER_PRI_NUM] = {
0, 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7, 7, 7};
@@ -828,7 +860,10 @@ int edma_setup(struct ppe_device *ppe_de
@@ -829,7 +861,10 @@ int edma_setup(struct ppe_device *ppe_de
edma_ctx->hw_info = &ipq9574_hw_info;
edma_ctx->ppe_dev = ppe_dev;
edma_ctx->rx_buf_size = rx_buff_size;

8
target/linux/qualcommbe/patches-6.18/0338-net-ethernet-qualcomm-Add-sysctl-for-RPS-bitmap.patch
View File

@ -1,4 +1,4 @@
From dcac735a715c13a817d65ae371564cf2793330b2 Mon Sep 17 00:00:00 2001
From 16a5c5c6725c07dcd4af0d565c2110a3d6264e8b Mon Sep 17 00:00:00 2001
From: Pavithra R <quic_pavir@quicinc.com>
Date: Tue, 11 Jun 2024 01:43:22 +0530
Subject: [PATCH] net: ethernet: qualcomm: Add sysctl for RPS bitmap
@ -20,7 +20,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
--- a/drivers/net/ethernet/qualcomm/ppe/edma.c
+++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
@@ -797,6 +797,11 @@ void edma_destroy(struct ppe_device *ppe
@@ -798,6 +798,11 @@ void edma_destroy(struct ppe_device *ppe
struct edma_ring_info *rx = hw_info->rx;
u32 i;
@ -32,7 +32,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/* Disable interrupts. */
for (i = 1; i <= hw_info->max_ports; i++)
edma_cfg_tx_disable_interrupts(i);
@@ -840,6 +845,17 @@ void edma_destroy(struct ppe_device *ppe
@@ -841,6 +846,17 @@ void edma_destroy(struct ppe_device *ppe
kfree(edma_ctx->netdev_arr);
}
@ -50,7 +50,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
/**
* edma_setup - EDMA Setup.
* @ppe_dev: PPE device
@@ -865,6 +881,13 @@ int edma_setup(struct ppe_device *ppe_de
@@ -866,6 +882,13 @@ int edma_setup(struct ppe_device *ppe_de
if (tx_requeue_stop != 0)
edma_ctx->tx_requeue_stop = true;

2
target/linux/qualcommbe/patches-6.18/0339-net-ethernet-qualcomm-Add-support-for-label-property.patch
View File

@ -1,4 +1,4 @@
From a809433c9b6a418dd886f12a5dcb3376f73bf2a7 Mon Sep 17 00:00:00 2001
From af28e89726909c52b5bfd55bd45ffa7934f3ca6b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 4 Dec 2024 01:37:05 +0100
Subject: [PATCH] net: ethernet: qualcomm: Add support for label property for

4
target/linux/qualcommbe/patches-6.18/0340-net-ethernet-qualcomm-ppe-Fix-unmet-dependency-with-.patch
View File

@ -1,4 +1,4 @@
From 9c4ad75f17788a64c1e37d0b9e19ca157e01c80a Mon Sep 17 00:00:00 2001
From 7e872efc79091d4b43983d10a28ba322195f9d76 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 9 Dec 2024 18:19:06 +0100
Subject: [PATCH] net: ethernet: qualcomm: ppe: Fix unmet dependency with
@ -20,7 +20,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
@@ -68,7 +68,6 @@ config QCOM_PPE
@@ -67,7 +67,6 @@ config QCOM_PPE
select REGMAP_MMIO
select PHYLINK
select PCS_QCOM_IPQ_UNIPHY

6
target/linux/qualcommbe/patches-6.18/0341-net-ethernet-qualcomm-ppe-select-correct-PCS-depende.patch
View File

@ -1,4 +1,4 @@
From ac41b401d274a4004027fa4000d801cd28c51f4c Mon Sep 17 00:00:00 2001
From e913a488e9c8f338488eaa5b3a88e10dffb4e7ee Mon Sep 17 00:00:00 2001
From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date: Tue, 13 May 2025 13:41:37 -0500
Subject: [PATCH] net: ethernet: qualcomm: ppe: select correct PCS dependency
@ -13,8 +13,8 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
@@ -67,7 +67,7 @@ config QCOM_PPE
depends on COMMON_CLK
@@ -66,7 +66,7 @@ config QCOM_PPE
depends on ARCH_QCOM || COMPILE_TEST
select REGMAP_MMIO
select PHYLINK
- select PCS_QCOM_IPQ_UNIPHY

3179
target/linux/qualcommbe/patches-6.18/0342-net-qualcomm-Update-IPQ9574-PPE-driver.patch Normal file
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File diff suppressed because it is too large Load Diff

11
target/linux/qualcommbe/patches-6.18/0343-arm64-dts-qcom-Add-IPQ9574-PPE-base-device-node.patch
View File

@ -1,4 +1,4 @@
From bbf706ecfd4295d73c8217d5220573dd51d7a081 Mon Sep 17 00:00:00 2001
From 2f31a177b001b99234b373afd2f8ba2d65b4c852 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Fri, 1 Mar 2024 14:46:45 +0800
Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 PPE base device node
@ -10,6 +10,7 @@ the UNIPHY (PCS).
Change-Id: I254bd48c218aa4eab54f697a2ad149f5a93b682c
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Alex G: Add "qcom_ppe" label to PPE node
Also include <qcom,ipq9574-nsscc.h> bindings
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 39 +++++++++++++++++++++++++++
@ -25,7 +26,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -1271,6 +1272,44 @@
@@ -1277,6 +1278,44 @@
#interconnect-cells = <1>;
};
@ -40,9 +41,9 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
+ <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>;
+ clock-names = "ppe",
+ "ppe_cfg",
+ "ppe_ipe",
+ "ppe_btq";
+ "apb",
+ "ipe",
+ "btq";
+ resets = <&nsscc PPE_FULL_RESET>;
+ interconnects = <&nsscc MASTER_NSSNOC_PPE
+ &nsscc SLAVE_NSSNOC_PPE>,

151
target/linux/qualcommbe/patches-6.18/0344-arm64-dts-qcom-Add-EDMA-node-for-IPQ9574.patch
View File

@ -1,4 +1,4 @@
From bd50babc7db2a35d98236a0386173dccd6c6374b Mon Sep 17 00:00:00 2001
From fc1fe4649dc62ecfffc94b76d908d66905d52e16 Mon Sep 17 00:00:00 2001
From: Pavithra R <quic_pavir@quicinc.com>
Date: Wed, 6 Mar 2024 22:29:41 +0530
Subject: [PATCH] arm64: dts: qcom: Add EDMA node for IPQ9574
@ -8,26 +8,35 @@ enable ethernet support.
Change-Id: I87d7c50f2485c8670948dce305000337f6499f8b
Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
Alex G: Add missing edma interrupts
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 68 +++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 139 ++++++++++++++++++++++++++
1 file changed, 139 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -1308,6 +1308,74 @@
@@ -1314,6 +1314,145 @@
"nssnoc_memnoc",
"memnoc_nssnoc",
"memnoc_nssnoc_1";
+
+ edma {
+ compatible = "qcom,ipq9574-edma";
+ ethernet-dma {
+ clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>,
+ <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>;
+ clock-names = "edma",
+ "edma-cfg";
+ clock-names = "sys",
+ "apb";
+ resets = <&nsscc EDMA_HW_RESET>;
+ reset-names = "edma_rst";
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ reset-names = "edma";
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
@ -51,40 +60,104 @@ Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma_txcmpl_8",
+ "edma_txcmpl_9",
+ "edma_txcmpl_10",
+ "edma_txcmpl_11",
+ "edma_txcmpl_12",
+ "edma_txcmpl_13",
+ "edma_txcmpl_14",
+ "edma_txcmpl_15",
+ "edma_txcmpl_16",
+ "edma_txcmpl_17",
+ "edma_txcmpl_18",
+ "edma_txcmpl_19",
+ "edma_txcmpl_20",
+ "edma_txcmpl_21",
+ "edma_txcmpl_22",
+ "edma_txcmpl_23",
+ "edma_txcmpl_24",
+ "edma_txcmpl_25",
+ "edma_txcmpl_26",
+ "edma_txcmpl_27",
+ "edma_txcmpl_28",
+ "edma_txcmpl_29",
+ "edma_txcmpl_30",
+ "edma_txcmpl_31",
+ "edma_rxdesc_20",
+ "edma_rxdesc_21",
+ "edma_rxdesc_22",
+ "edma_rxdesc_23",
+ "edma_misc";
+ interrupt-names = "txcmpl_0",
+ "txcmpl_1",
+ "txcmpl_2",
+ "txcmpl_3",
+ "txcmpl_4",
+ "txcmpl_5",
+ "txcmpl_6",
+ "txcmpl_7",
+ "txcmpl_8",
+ "txcmpl_9",
+ "txcmpl_10",
+ "txcmpl_11",
+ "txcmpl_12",
+ "txcmpl_13",
+ "txcmpl_14",
+ "txcmpl_15",
+ "txcmpl_16",
+ "txcmpl_17",
+ "txcmpl_18",
+ "txcmpl_19",
+ "txcmpl_20",
+ "txcmpl_21",
+ "txcmpl_22",
+ "txcmpl_23",
+ "txcmpl_24",
+ "txcmpl_25",
+ "txcmpl_26",
+ "txcmpl_27",
+ "txcmpl_28",
+ "txcmpl_29",
+ "txcmpl_30",
+ "txcmpl_31",
+ "rxfill_0",
+ "rxfill_1",
+ "rxfill_2",
+ "rxfill_3",
+ "rxfill_4",
+ "rxfill_5",
+ "rxfill_6",
+ "rxfill_7",
+ "rxdesc_0",
+ "rxdesc_1",
+ "rxdesc_2",
+ "rxdesc_3",
+ "rxdesc_4",
+ "rxdesc_5",
+ "rxdesc_6",
+ "rxdesc_7",
+ "rxdesc_8",
+ "rxdesc_9",
+ "rxdesc_10",
+ "rxdesc_11",
+ "rxdesc_12",
+ "rxdesc_13",
+ "rxdesc_14",
+ "rxdesc_15",
+ "rxdesc_16",
+ "rxdesc_17",
+ "rxdesc_18",
+ "rxdesc_19",
+ "rxdesc_20",
+ "rxdesc_21",
+ "rxdesc_22",
+ "rxdesc_23",
+ "misc";
+ };
};

8
target/linux/qualcommbe/patches-6.18/0345-arm64-dts-qcom-Add-IPQ9574-MDIO-device-node.patch
View File

@ -1,4 +1,4 @@
From 657833a74f532262d415fa2ca354b69f4a97353c Mon Sep 17 00:00:00 2001
From 77b24a2ce99bc8d23aacbd101b28e57b7b79f406 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Thu, 23 Nov 2023 15:41:20 +0800
Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 MDIO device node
@ -15,16 +15,16 @@ Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -295,6 +295,8 @@
@@ -297,6 +297,8 @@
mdio: mdio@90000 {
compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio";
reg = <0x00090000 0x64>;
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_MDIO_AHB_CLK>;
@@ -414,6 +416,22 @@
@@ -416,6 +418,22 @@
interrupt-controller;
#interrupt-cells = <2>;

6
target/linux/qualcommbe/patches-6.18/0346-arm64-dts-qcom-ipq9574-Use-usb-phy-for-node-names.patch
View File

@ -1,4 +1,4 @@
From 91467ca0db1654644b2168f882f223d47dcfb9c1 Mon Sep 17 00:00:00 2001
From 263449c0667a03f366c801cf240e64ca0b464d47 Mon Sep 17 00:00:00 2001
From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date: Sat, 30 Mar 2024 20:03:30 -0500
Subject: [PATCH] arm64: dts: qcom: ipq9574: Use 'usb-phy' for node names
@ -14,7 +14,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -720,7 +720,7 @@
@@ -722,7 +722,7 @@
status = "disabled";
};
@ -23,7 +23,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
compatible = "qcom,ipq9574-qusb2-phy";
reg = <0x0007b000 0x180>;
#phy-cells = <0>;
@@ -734,7 +734,7 @@
@@ -736,7 +736,7 @@
status = "disabled";
};

2
target/linux/qualcommbe/patches-6.18/0347-arm64-dts-qcom-ipq9574-add-QPIC-SPI-NAND-default-par.patch
View File

@ -1,4 +1,4 @@
From be44d0251a2540f3b8d7205e0bc6659704366711 Mon Sep 17 00:00:00 2001
From 8079928b433ff21a39423a7d9233d76d8b6d91aa Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 30 Jan 2025 00:39:30 +0100
Subject: [PATCH] arm64: dts: qcom: ipq9574: add QPIC SPI NAND default

13
target/linux/qualcommbe/patches-6.18/0348-arm64-dts-qcom-add-partition-table-for-ipq9574-rdp-c.patch
View File

@ -1,4 +1,4 @@
From 47c7ae9715d76054d98e8407dbb8ca1cf42fd587 Mon Sep 17 00:00:00 2001
From 7e6bf071e4efa66e24feba27619e17eb3c71251d Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 9 Dec 2024 17:50:31 +0100
Subject: [PATCH] arm64: dts: qcom: add partition table for ipq9574 rdp common
@ -12,7 +12,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
@@ -74,11 +74,158 @@
@@ -74,11 +74,155 @@
status = "okay";
flash@0 {
@ -125,15 +125,12 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+ };
+
+ partition@530000 {
+ compatible = "u-boot,env";
+ label = "0:appsblenv";
+ reg = <0x530000 0x10000>;
+
+ nvmem-layout {
+ compatible = "u-boot,env";
+
+ macaddr_lan: ethaddr {
+ #nvmem-cell-cells = <1>;
+ };
+ macaddr_lan: ethaddr {
+ #nvmem-cell-cells = <1>;
+ };
+ };
+

78
target/linux/qualcommbe/patches-6.18/0349-arm64-dts-qcom-Add-IPQ9574-RDP433-port-node.patch
View File

@ -1,4 +1,4 @@
From 001b663ecc5f838dac143623badae0e472749d8a Mon Sep 17 00:00:00 2001
From c5a3d88f12a7ac9546f5ead061212f06ebaab740 Mon Sep 17 00:00:00 2001
From: Lei Wei <quic_leiwei@quicinc.com>
Date: Tue, 14 May 2024 10:53:27 +0800
Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 RDP433 port node
@ -11,6 +11,8 @@ channel0.
Change-Id: Ic16efdef2fe2cff7b1e80245619c0f82afb24cb9
Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
Alex G: Use "pcs<n>_ch0" labels instead of "pcsuniphy<n>_ch0"
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 167 ++++++++++++++++++++
1 file changed, 167 insertions(+)
@ -64,7 +66,7 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
&tlmm {
pcie1_default: pcie1-default-state {
@@ -161,3 +201,130 @@
@@ -129,3 +169,130 @@
};
};
};
@ -83,15 +85,15 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+ clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
+ <&nsscc NSS_CC_PORT1_RX_CLK>,
+ <&nsscc NSS_CC_PORT1_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ clock-names = "mac",
+ "rx",
+ "tx";
+ resets = <&nsscc PORT1_MAC_ARES>,
+ <&nsscc PORT1_RX_ARES>,
+ <&nsscc PORT1_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ reset-names = "mac",
+ "rx",
+ "tx";
+ };
+
+ port@2 {
@ -103,15 +105,15 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+ clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
+ <&nsscc NSS_CC_PORT2_RX_CLK>,
+ <&nsscc NSS_CC_PORT2_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ clock-names = "mac",
+ "rx",
+ "tx";
+ resets = <&nsscc PORT2_MAC_ARES>,
+ <&nsscc PORT2_RX_ARES>,
+ <&nsscc PORT2_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ reset-names = "mac",
+ "rx",
+ "tx";
+ };
+
+ port@3 {
@ -123,15 +125,15 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+ clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
+ <&nsscc NSS_CC_PORT3_RX_CLK>,
+ <&nsscc NSS_CC_PORT3_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ clock-names = "mac",
+ "rx",
+ "tx";
+ resets = <&nsscc PORT3_MAC_ARES>,
+ <&nsscc PORT3_RX_ARES>,
+ <&nsscc PORT3_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ reset-names = "mac",
+ "rx",
+ "tx";
+ };
+
+ port@4 {
@ -143,15 +145,15 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+ clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
+ <&nsscc NSS_CC_PORT4_RX_CLK>,
+ <&nsscc NSS_CC_PORT4_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ clock-names = "mac",
+ "rx",
+ "tx";
+ resets = <&nsscc PORT4_MAC_ARES>,
+ <&nsscc PORT4_RX_ARES>,
+ <&nsscc PORT4_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ reset-names = "mac",
+ "rx",
+ "tx";
+ };
+
+ port@5 {
@ -163,15 +165,15 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+ clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
+ <&nsscc NSS_CC_PORT5_RX_CLK>,
+ <&nsscc NSS_CC_PORT5_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ clock-names = "mac",
+ "rx",
+ "tx";
+ resets = <&nsscc PORT5_MAC_ARES>,
+ <&nsscc PORT5_RX_ARES>,
+ <&nsscc PORT5_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ reset-names = "mac",
+ "rx",
+ "tx";
+ };
+
+ port@6 {
@ -183,15 +185,15 @@ Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
+ clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
+ <&nsscc NSS_CC_PORT6_RX_CLK>,
+ <&nsscc NSS_CC_PORT6_TX_CLK>;
+ clock-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ clock-names = "mac",
+ "rx",
+ "tx";
+ resets = <&nsscc PORT6_MAC_ARES>,
+ <&nsscc PORT6_RX_ARES>,
+ <&nsscc PORT6_TX_ARES>;
+ reset-names = "port_mac",
+ "port_rx",
+ "port_tx";
+ reset-names = "mac",
+ "rx",
+ "tx";
+ };
+ };
+};

2
target/linux/qualcommbe/patches-6.18/0350-arm64-dts-qcom-add-AQR-NVMEM-node-for-IPQ9574-RDP433.patch
View File

@ -1,4 +1,4 @@
From 30b751f5984e295f0b5e7a2308b6103fae3322d2 Mon Sep 17 00:00:00 2001
From b6155e23c6c350b528a0d64dc667fefb0a5acbf6 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 9 Dec 2024 18:10:43 +0100
Subject: [PATCH] arm64: dts: qcom: add AQR NVMEM node for IPQ9574 RDP433 board

14
target/linux/qualcommbe/patches-6.18/0351-arm64-dts-qcom-Add-label-to-EDMA-port-for-IPQ9574-RD.patch
View File

@ -1,4 +1,4 @@
From b297d12d434191845cf8ae359466dcd8312ed21d Mon Sep 17 00:00:00 2001
From 88480bcfb5a5444602b5b7019a2005a9b010cb34 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 4 Dec 2024 01:49:09 +0100
Subject: [PATCH] arm64: dts: qcom: Add label to EDMA port for IPQ9574 RDP433
@ -12,7 +12,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
@@ -217,6 +217,7 @@
@@ -185,6 +185,7 @@
reg = <1>;
phy-mode = "qsgmii";
managed = "in-band-status";
@ -20,7 +20,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
phy-handle = <&phy0>;
pcs-handle = <&pcs0_ch0>;
clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
@@ -237,6 +238,7 @@
@@ -205,6 +206,7 @@
reg = <2>;
phy-mode = "qsgmii";
managed = "in-band-status";
@ -28,7 +28,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
phy-handle = <&phy1>;
pcs-handle = <&pcs0_ch1>;
clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
@@ -257,6 +259,7 @@
@@ -225,6 +227,7 @@
reg = <3>;
phy-mode = "qsgmii";
managed = "in-band-status";
@ -36,7 +36,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
phy-handle = <&phy2>;
pcs-handle = <&pcs0_ch2>;
clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
@@ -277,6 +280,7 @@
@@ -245,6 +248,7 @@
reg = <4>;
phy-mode = "qsgmii";
managed = "in-band-status";
@ -44,7 +44,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
phy-handle = <&phy3>;
pcs-handle = <&pcs0_ch3>;
clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
@@ -297,6 +301,7 @@
@@ -265,6 +269,7 @@
reg = <5>;
phy-mode = "usxgmii";
managed = "in-band-status";
@ -52,7 +52,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
phy-handle = <&phy4>;
pcs-handle = <&pcs1_ch0>;
clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
@@ -317,6 +322,7 @@
@@ -285,6 +290,7 @@
reg = <6>;
phy-mode = "usxgmii";
managed = "in-band-status";

2
target/linux/qualcommbe/patches-6.18/0352-clk-qcom-nsscc-Attach-required-NSSNOC-clock-to-PM-do.patch
View File

@ -1,4 +1,4 @@
From 6417cb20e854194a845d4ab092b92fd753c0e405 Mon Sep 17 00:00:00 2001
From acbd594bd043db9df90394f40e503143637a5f3e Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 30 Jan 2025 16:11:14 +0100
Subject: [PATCH] clk: qcom: nsscc: Attach required NSSNOC clock to PM domain

6
target/linux/qualcommbe/patches-6.18/0353-arm64-dts-qcom-ipq9574-add-NSSNOC-clock-to-nss-node.patch
View File

@ -1,4 +1,4 @@
From 372bbae100ffe14908bfd8448143c6cdbea17e8d Mon Sep 17 00:00:00 2001
From 7767d4651734a63576282cdbd93a5a7e7318d557 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Thu, 30 Jan 2025 16:23:03 +0100
Subject: [PATCH] arm64: dts: qcom: ipq9574: add NSSNOC clock to nss node
@ -16,7 +16,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -1255,7 +1255,10 @@
@@ -1279,7 +1279,10 @@
<&pcs1 1>,
<&pcs2 0>,
<&pcs2 1>,
@ -28,7 +28,7 @@ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
clock-names = "xo",
"nss_1200",
"ppe_353",
@@ -1266,7 +1269,10 @@
@@ -1290,7 +1293,10 @@
"uniphy1_tx",
"uniphy2_rx",
"uniphy2_tx",

2
target/linux/qualcommbe/patches-6.18/0354-clk-qcom-nsscc-ipq9574-fix-port5-clock-config.patch
View File

@ -1,4 +1,4 @@
From fa691ff57c72a8f0bfeff1a9e86ae2d78765b0da Mon Sep 17 00:00:00 2001
From 5cd1a878418e3efb544b2f1e0117d1c9d8238bfe Mon Sep 17 00:00:00 2001
From: Mantas Pucka <mantas@8devices.com>
Date: Mon, 31 Mar 2025 15:39:59 +0300
Subject: [PATCH] clk: qcom: nsscc-ipq9574: fix port5 clock config

30
target/linux/qualcommbe/patches-6.18/0355-arm64-dts-qcom-ipq9574-add-NSSNOC-interconnects-to-n.patch Normal file
View File

@ -0,0 +1,30 @@
From 3ad6cba1ae540622afbe1f8250af23b2e1a51cde Mon Sep 17 00:00:00 2001
From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Date: Sun, 18 May 2025 21:11:16 -0500
Subject: [PATCH] arm64: dts: qcom: ipq9574: add NSSNOC interconnects to nsssc
node
Add the interconnects to the nsscc clock controller node. I don't
remember exactly what problem I was solving. Without this change, the
ethernet PPE driver gets an -EINVAL from phyling when connecting to a
QCA8084 phy. Exact mechanism unknown, but this fixes it.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -1300,6 +1300,11 @@
#clock-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
+
+
+ interconnects = <&gcc MASTER_NSSNOC_NSSCC &gcc SLAVE_NSSNOC_NSSCC>,
+ <&gcc MASTER_NSSNOC_SNOC_0 &gcc SLAVE_NSSNOC_SNOC_0>,
+ <&gcc MASTER_NSSNOC_SNOC_1 &gcc SLAVE_NSSNOC_SNOC_1>;
};
qcom_ppe: ethernet@3a000000 {