809ca978d1
Generate new patches for 6.18 from my ipq95xx development branch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21506 Signed-off-by: Robert Marko <robimarko@gmail.com>
31 lines
1.0 KiB
Diff
31 lines
1.0 KiB
Diff
From 3ad6cba1ae540622afbe1f8250af23b2e1a51cde Mon Sep 17 00:00:00 2001
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From: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Date: Sun, 18 May 2025 21:11:16 -0500
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Subject: [PATCH] arm64: dts: qcom: ipq9574: add NSSNOC interconnects to nsssc
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node
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Add the interconnects to the nsscc clock controller node. I don't
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remember exactly what problem I was solving. Without this change, the
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ethernet PPE driver gets an -EINVAL from phyling when connecting to a
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QCA8084 phy. Exact mechanism unknown, but this fixes it.
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -1300,6 +1300,11 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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#interconnect-cells = <1>;
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+
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+
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+ interconnects = <&gcc MASTER_NSSNOC_NSSCC &gcc SLAVE_NSSNOC_NSSCC>,
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+ <&gcc MASTER_NSSNOC_SNOC_0 &gcc SLAVE_NSSNOC_SNOC_0>,
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+ <&gcc MASTER_NSSNOC_SNOC_1 &gcc SLAVE_NSSNOC_SNOC_1>;
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};
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qcom_ppe: ethernet@3a000000 {
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