809ca978d1
Generate new patches for 6.18 from my ipq95xx development branch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21506 Signed-off-by: Robert Marko <robimarko@gmail.com>
137 lines
3.9 KiB
Diff
137 lines
3.9 KiB
Diff
From 827dda24d66b1ecfaa4981b6fe505cedf0579e51 Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Wed, 6 Mar 2024 17:40:52 +0800
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Subject: [PATCH] net: pcs: Add 10GBASER interface mode support to IPQ UNIPHY
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PCS driver
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10GBASER mode is used when PCS connects with a 10G SFP module.
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Change-Id: Ifc3c3bb23811807a9b34e88771aab2c830c2327c
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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Alex G: Use regmap to read/write registers
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Remove xpcs_reset deassert logic (to be implemented later)
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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drivers/net/pcs/pcs-qcom-ipq9574.c | 47 ++++++++++++++++++++++++++++++
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1 file changed, 47 insertions(+)
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--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
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@@ -55,6 +55,9 @@
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FIELD_PREP(GENMASK(9, 2), \
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FIELD_GET(XPCS_INDIRECT_ADDR_L, reg)))
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+#define XPCS_KR_STS 0x30020
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+#define XPCS_KR_LINK_STS BIT(12)
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+
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#define XPCS_DIG_CTRL 0x38000
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#define XPCS_USXG_ADPT_RESET BIT(10)
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#define XPCS_USXG_EN BIT(9)
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@@ -196,6 +199,28 @@ static void ipq_pcs_get_state_usxgmii(st
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state->duplex = DUPLEX_FULL;
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}
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+static void ipq_pcs_get_state_10gbaser(struct ipq_pcs *qpcs,
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+ struct phylink_link_state *state)
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+{
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+ unsigned int val;
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+ int ret;
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+
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+ ret = regmap_read(qpcs->regmap, XPCS_KR_STS, &val);
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+ if (ret) {
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+ state->link = 0;
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+ return;
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+ }
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+
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+ state->link = !!(val & XPCS_KR_LINK_STS);
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+
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+ if (!state->link)
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+ return;
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+
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+ state->speed = SPEED_10000;
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+ state->duplex = DUPLEX_FULL;
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+ state->pause |= MLO_PAUSE_TXRX_MASK;
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+}
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+
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static int ipq_pcs_config_mode(struct ipq_pcs *qpcs,
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phy_interface_t interface)
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{
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@@ -212,6 +237,7 @@ static int ipq_pcs_config_mode(struct ip
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val = PCS_MODE_QSGMII;
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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val = PCS_MODE_XPCS;
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rate = 312500000;
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break;
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@@ -311,6 +337,15 @@ static int ipq_pcs_config_usxgmii(struct
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return regmap_set_bits(qpcs->regmap, XPCS_MII_CTRL, XPCS_MII_AN_EN);
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}
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+static int ipq_pcs_config_10gbaser(struct ipq_pcs *qpcs)
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+{
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+ /* Configure 10GBASER mode if required */
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+ if (qpcs->interface == PHY_INTERFACE_MODE_10GBASER)
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+ return 0;
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+
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+ return ipq_pcs_config_mode(qpcs, PHY_INTERFACE_MODE_10GBASER);
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+}
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+
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static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs,
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int index,
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unsigned int neg_mode,
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@@ -399,6 +434,7 @@ static int ipq_pcs_validate(struct phyli
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switch (state->interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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return 0;
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case PHY_INTERFACE_MODE_USXGMII:
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/* USXGMII only supports full duplex mode */
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@@ -418,6 +454,8 @@ static unsigned int ipq_pcs_inband_caps(
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ return LINK_INBAND_DISABLE;
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default:
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return 0;
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}
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@@ -472,6 +510,9 @@ static void ipq_pcs_get_state(struct phy
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case PHY_INTERFACE_MODE_USXGMII:
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ipq_pcs_get_state_usxgmii(qpcs, state);
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break;
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ ipq_pcs_get_state_10gbaser(qpcs, state);
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+ break;
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default:
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break;
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}
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@@ -500,6 +541,8 @@ static int ipq_pcs_config(struct phylink
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return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface);
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case PHY_INTERFACE_MODE_USXGMII:
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return ipq_pcs_config_usxgmii(qpcs);
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ return ipq_pcs_config_10gbaser(qpcs);
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default:
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return -EOPNOTSUPP;
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};
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@@ -524,6 +567,9 @@ static void ipq_pcs_link_up(struct phyli
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case PHY_INTERFACE_MODE_USXGMII:
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ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed);
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break;
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ /* Nothing to do here */
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+ return;
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default:
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return;
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}
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@@ -603,6 +649,7 @@ static unsigned long ipq_pcs_clk_rate_ge
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{
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switch (qpcs->interface) {
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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return 312500000;
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default:
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return 125000000;
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