openwrt/target/linux/qualcommbe/patches-6.18/0308-net-phy-qca808x-Add-QCA8084-package-init-function.patch

From 7da15e71be92f1db476f631642cd1eb590102a43 Mon Sep 17 00:00:00 2001
From: Luo Jie <quic_luoj@quicinc.com>
Date: Thu, 25 Jan 2024 17:13:24 +0800
Subject: [PATCH] net: phy: qca808x: Add QCA8084 package init function

The package mode of PHY is configured for the interface mode of two
PCSes working correctly.

The PHY package level clocks are enabled and their rates configured.

Change-Id: I63d4b22d2a70ee713cc6a6818b0f3c7aa098a5f5
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Alex G: Use phy_package_get_*() accessors
        Update to match the patches that will be upstream.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
---
 drivers/net/phy/qcom/qca808x.c | 118 +++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 
+#include <dt-bindings/net/qcom,qca808x.h>
 #include <linux/phy.h>
 #include <linux/module.h>
 #include <linux/of.h>
@@ -146,6 +147,12 @@
 #define QCA8084_EPHY_ADDR3_MASK			GENMASK(19, 15)
 #define QCA8084_EPHY_LDO_EN			GENMASK(21, 20)
 
+#define QCA8084_WORK_MODE_CFG			0xc90f030
+#define QCA8084_WORK_MODE_MASK			GENMASK(5, 0)
+#define QCA8084_WORK_MODE_QXGMII		(BIT(5) | GENMASK(3, 0))
+#define QCA8084_WORK_MODE_SWITCH		BIT(4)
+#define QCA8084_WORK_MODE_SWITCH_PORT4_SGMII	BIT(5)
+
 MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
 MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
 MODULE_LICENSE("GPL");
@@ -169,6 +176,7 @@ struct qca808x_priv {
 };
 
 struct qca808x_shared_priv {
+	int package_mode;
 	struct clk *clk[PACKAGE_CLK_MAX];
 };
 
@@ -837,10 +845,111 @@ static void qca808x_get_phy_stats(struct
 	qcom_phy_get_stats(stats, priv->hw_stats);
 }
 
+static int qca8084_package_clock_init(struct qca808x_shared_priv *shared_priv)
+{
+	int ret;
+
+	/* Configure clock rate 312.5MHZ for the PHY package
+	 * APB bridge clock tree.
+	 */
+	ret = clk_set_rate(shared_priv->clk[APB_BRIDGE_CLK], 312500000);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[SWITCH_CORE_CLK]);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[APB_BRIDGE_CLK]);
+	if (ret)
+		return ret;
+
+	/* Configure clock rate 104.17MHZ for the PHY package
+	 * AHB clock tree.
+	 */
+	ret = clk_set_rate(shared_priv->clk[AHB_CLK], 104170000);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[AHB_CLK]);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[SEC_CTRL_AHB_CLK]);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[TLMM_CLK]);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[TLMM_AHB_CLK]);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[CNOC_AHB_CLK]);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(shared_priv->clk[MDIO_MASTER_AHB_CLK]);
+	if (ret)
+		return ret;
+
+	return clk_prepare_enable(shared_priv->clk[MDIO_AHB_CLK]);
+}
+
+static int qca8084_phy_package_config_init_once(struct phy_device *phydev)
+{
+	struct qca808x_shared_priv *shared_priv;
+	int ret, mode;
+
+	shared_priv = phy_package_get_priv(phydev);
+	switch (shared_priv->package_mode) {
+	case QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED:
+		mode = QCA8084_WORK_MODE_QXGMII;
+		break;
+	case QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_MAC:
+		mode = QCA8084_WORK_MODE_SWITCH;
+		break;
+	case QCA808X_PCS1_SGMII_MAC_PCS0_SGMII_PHY:
+		mode = QCA8084_WORK_MODE_SWITCH_PORT4_SGMII;
+		break;
+	default:
+		phydev_err(phydev, "Invalid qcom,package-mode %d\n",
+			   shared_priv->package_mode);
+		return -EINVAL;
+	}
+
+	ret = qca8084_mii_modify(phydev, QCA8084_WORK_MODE_CFG,
+				 QCA8084_WORK_MODE_MASK,
+				 FIELD_PREP(QCA8084_WORK_MODE_MASK, mode));
+	if (ret)
+		return ret;
+
+	/* Enable efuse loading into analog circuit */
+	ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG,
+				 QCA8084_EPHY_LDO_EN, 0);
+	if (ret)
+		return ret;
+
+	usleep_range(10000, 11000);
+
+	/* Initialize the PHY package clock and reset, which is the
+	 * necessary config sequence after GPIO reset on the PHY package.
+	 */
+	return qca8084_package_clock_init(shared_priv);
+}
+
 static int qca8084_config_init(struct phy_device *phydev)
 {
 	int ret;
 
+	if (phy_package_init_once(phydev)) {
+		ret = qca8084_phy_package_config_init_once(phydev);
+		if (ret)
+			return ret;
+	}
+
 	if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
 		__set_bit(PHY_INTERFACE_MODE_10G_QXGMII,
 			  phydev->possible_interfaces);
@@ -975,6 +1084,15 @@ static int qca8084_phy_package_probe_onc
 		shared_priv->clk[i] = clk;
 	}
 
+	/* The package mode 10G-QXGMII of PCS1 is used for Quad PHY and
+	 * PCS0 is unused by default.
+	 */
+	shared_priv->package_mode = QCA808X_PCS1_10G_QXGMII_PCS0_UNUNSED;
+	ret = of_property_read_u32(np, "qcom,package-mode",
+				   &shared_priv->package_mode);
+	if (ret && ret != -EINVAL)
+		return ret;
+
 	rstc = of_reset_control_get_exclusive(np, NULL);
 	if (IS_ERR(rstc))
 		return dev_err_probe(&phydev->mdio.dev, PTR_ERR(rstc),