openwrt/target/linux/econet/dts/en751627.dtsi

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;

#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
#include <dt-bindings/reset/airoha,en7523-reset.h>

/ {
	compatible = "econet,en751627";
	#address-cells = <1>;
	#size-cells = <1>;

	hpt_clock: clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;  /* 200 MHz */
	};

	spi_clock: spi-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <40000000>;  /* 40 MHz */
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "mips,mips1004Kc";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "mips,mips1004Kc";
			reg = <1>;
		};
	};

	cpuintc: interrupt-controller {
		compatible = "mti,cpu-interrupt-controller";
		interrupt-controller;
		#address-cells = <0>;
		#interrupt-cells = <1>;
	};

	gic: interrupt-controller@1f8c0000 {
		compatible = "mti,gic";
		reg = <0x1f8c0000 0x20000>;

		interrupt-controller;
		#interrupt-cells = <3>;

		interrupt-parent = <&cpuintc>;
		interrupts = <2>;
	};

	pcie_phy0: pcie-phy@1faf2000 {
		compatible = "econet,en7528-pcie-phy1";
		reg = <0x1faf2000 0x1000>;
		#phy-cells = <0>;
	};

	pcie_phy1: pcie-phy@1fac0000 {
		compatible = "econet,en7528-pcie-phy1";
		reg = <0x1fac0000 0x1000>;
		#phy-cells = <0>;
	};

	gpio0: gpio@1fbf0200 {
		compatible = "airoha,en7523-gpio";
		reg = <0x1fbf0204 0x4>,
		      <0x1fbf0200 0x4>,
		      <0x1fbf0220 0x4>,
		      <0x1fbf0214 0x4>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	gpio1: gpio@1fbf0270 {
		compatible = "airoha,en7523-gpio";
		reg = <0x1fbf0270 0x4>,
		      <0x1fbf0260 0x4>,
		      <0x1fbf0264 0x4>,
		      <0x1fbf0278 0x4>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	scu: system-controller@1fb00000 {
		compatible = "airoha,en7523-scu";
		reg = <0x1fa20000 0x400>,
		      <0x1fb00000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	timer_hpt: timer@1fbf0400 {
		compatible = "econet,en7528-timer";
		reg = <0x1fbf0400 0x14>,
		      <0x1fbe0000 0x14>;

		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&hpt_clock>;
	};

	spi_ctrl: spi@1fa10000 {
		compatible = "airoha,en7581-snand";
		reg = <0x1fa10000 0x140>,
		      <0x1fa11000 0x160>;

		clocks = <&spi_clock>;
		clock-names = "spi";

		#address-cells = <1>;
		#size-cells = <0>;

		nand: nand@0 {
			compatible = "spi-nand";
			reg = <0>;
			spi-max-frequency = <40000000>;
			spi-tx-bus-width = <1>;
			spi-rx-bus-width = <2>;
		};
	};

	uart: serial@1fbf0000 {
		compatible = "airoha,en7523-uart";
		reg = <0x1fbf0000 0x30>;
		reg-io-width = <4>;
		reg-shift = <2>;

		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;

		clock-frequency = <7372800>;
	};

	pciecfg: pciecfg@1fb80000 {
		compatible = "mediatek,generic-pciecfg", "syscon";
		reg = <0x1fb80000 0x1000>;
	};

	pcie0: pcie@1fb81000 {
		compatible = "econet,en7528-pcie";
		device_type = "pci";
		reg = <0x1fb81000 0x1000>;
		reg-names = "port0";
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pcie_irq";
		clocks = <&scu EN7523_CLK_PCIE>;
		clock-names = "sys_ck0";
		phys = <&pcie_phy0>;
		phy-names = "pcie-phy0";
		bus-range = <0x00 0xff>;
		ranges = <0x01000000 0 0x00000000 0x1f600000 0 0x00010000>,
			 <0x82000000 0 0x20000000 0x20000000 0 0x08000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
				<0 0 0 2 &pcie_intc0 1>,
				<0 0 0 3 &pcie_intc0 2>,
				<0 0 0 4 &pcie_intc0 3>;

		pcie_intc0: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};

		slot0: pcie@0,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges;
		};
	};

	pcie1: pcie@1fb83000 {
		compatible = "econet,en7528-pcie";
		device_type = "pci";
		reg = <0x1fb83000 0x1000>;
		reg-names = "port1";
		linux,pci-domain = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pcie_irq";
		clocks = <&scu EN7523_CLK_PCIE>;
		clock-names = "sys_ck1";
		phys = <&pcie_phy1>;
		phy-names = "pcie-phy1";
		bus-range = <0x00 0xff>;
		ranges = <0x01000000 0 0x00000000 0x1f610000 0 0x00010000>,
			 <0x82000000 0 0x28000000 0x28000000 0 0x08000000>;
		status = "disabled";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
				<0 0 0 2 &pcie_intc1 1>,
				<0 0 0 3 &pcie_intc1 2>,
				<0 0 0 4 &pcie_intc1 3>;

		pcie_intc1: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};

		slot1: pcie@1,0 {
			reg = <0x0800 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges;
		};
	};

	usb: usb@1fb90000 {
		compatible = "mediatek,mt8173-xhci", "mediatek,mtk-xhci";
		reg = <0x1fb90000 0x4000>,
			<0x1fa80700 0x100>;
		reg-names = "mac", "ippc";

		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 17 IRQ_TYPE_LEVEL_HIGH>;
		usb3-lpm-capable;
	};
};